M48T128 ST Microelectronics, M48T128 Datasheet - Page 3

• Manufacturer Part Number: M48T128
• Description: 3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM
• Manufacturer: ST Microelectronics

Table 3. Operating Modes
Note: 1. X = V
READ MODE
The M48T128Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 131,072
bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within t
address input signal is stable, providing the E and
G access times are also satisfied. If the E and G
access times are not met, valid data will be avail-
able after the latter of the Chip Enable Access
Times (t
(t
signals is controlled by E and G. If the outputs are
activated before t
to an indeterminate state until t
dress Inputs are changed while E and G remain
active, output data will remain valid for t
put Data Hold Time) but will go indeterminate until
the next Address Access.
WRITE MODE
The M48T128Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W or E. A write is terminated by the
earlier rising edge of W or E. The addresses must
be held valid throughout the cycle. E or W must re-
turn high for a minimum of t
or t
another read or write cycle. Data-in must be valid
t
t
write cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G a low on W will disable the outputs t
ter W falls.
DVWH
WHDX
Deselect
Write
Read
Read
Deselect
Deselect
GLQV
WHAX
Mode
2. See Table 7 for details.
). The state of the eight three-state Data I/O
prior to the end of write and remain valid for
AVQV
afterward. G should be kept high during
ELQV
from Write Enable prior to the initiation of
IH
(Address Access Time) after the last
or V
) or Output Enable Access Time
IL
V
AVQV
; V
SO
SO
4.5V to 5.5V
3.0V to 3.6V
to V
= Battery Back-up Switchover Voltage.
, the data lines will be driven
V
V
PFD
or
SO
CC
EHAX
(2)
(1)
(min)
from Chip Enable
AVQV
(2)
. If the Ad-
AXQX
WLQZ
V
V
V
V
E
X
X
(Out-
IH
IL
IL
IL
af-
V
V
G
X
X
X
X
IH
IL
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Figure 3. AC Testing Load Circuit
Note: 1. 50pF for M48T128V (3.3V).
DATA RETENTION MODE
With valid V
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically deselect, write protecting itself when
V
dow. All outputs become high impedance and all
inputs are treated as "don't care".
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
CC
C L includes JIG capacitance
2. Excluding open drain output pins.
falls between V
DEVICE
UNDER
TEST
V
V
V
W
X
X
X
IH
IH
IL
CC
applied, the M48T128Y/V operates
DQ0-DQ7
High Z
High Z
High Z
High Z
D
D
OUT
IN
PFD
M48T128Y, M48T128V
C L = 100pF
(max), V
650
or 50pF
Battery Back-up Mode
CMOS Standby
(1)
Standby
Power
PFD
Active
Active
Active
(2)
(min) win-
0 to 3V
AI03630
1.5V
5ns
1.75V
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