X1226 Xicor, X1226 Datasheet - Page 6

• Manufacturer Part Number: X1226
• Description: Real Time Clock/Calendar with EEPROM
• Manufacturer: Xicor

X1226
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and
memory array during a write operation. This bit is a
volatile latch that powers up in the LOW (disabled)
state. While the WEL bit is LOW, writes to the CCR or
any array address will be ignored (no acknowledge will
be issued after the Data Byte). The WEL bit is set by
writing a “1” to the WEL bit and zeroes to the other bits
of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit
and zeroes to the other bits of the Status Register) or
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware (X1226 inter-
nally) when the device powers up after having lost all
power to the device. The bit is set regardless of
whether V
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3.
INTERRUPT CONTROL AND FREQUENCY
OUTPUT REGISTER (INT)
Interrupt Control and Status Bits (IM, AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either the
AL1E and AL0E bits are set to ‘1’, respectively.
REV 1.1.24 1/13/03
CC
or V
BACK
is applied first. The loss of only
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Table 3. Block Protect Bits
Two volatile bits (AL1 and AL0), associated with the two
alarms respectively, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the IRQ interrupt is enabled. The AL1 and AL0
bits in the status register are reset by the falling edge of
the eighth clock of a read of the register containing the
bits.
Pulse Interrupt Mode
The pulsed interrrupt mode allows for repetitive or
recurring alarm functionality. Hence an repetitive or
recurring alarm can be set for every n
minute, or n
the week. The pulsed interrupt mode can be consid-
ered a repetitive interrupt mode, with the repetition
rate set by the time setting fo the alarm.
The Pulse Interrupt Mode is enabled when the IM bit is
set.
The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.
Programmable Frequency Output Bits—FO1, FO0
These are two output control bits. They select one of
three divisions of the internal oscillator, that is applied
to the PHZ output pin. Table 4 shows the selection bits
for this output. When using the PHZ output function,
the Alarm IRQ output function is disabled.
IM Bit
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
Single Time Event Set By Alarm
Repetitive / Recurring Time Event Set By
Alarm
th
0
1
0
1
0
1
0
1
hour, or n
Interrupt / Alarm Frequency
Characteristics subject to change without notice.
6000h – 7FFFh
4000h – 7FFFh
0000h – 7FFFh
0000h – 00FFh
0000h – 01FFh
0000h – 03FFh
0000h – 007Fh
Addresses
Protected
X1226
None
th
date, or for the same day of
th
Array Lock
First 8 Pgs
First 2 pgs
First 4 pgs
First Page
second, or n
Upper 1/4
Upper 1/2
Full Array
None
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