X1226 Xicor, X1226 Datasheet - Page 7

• Manufacturer Part Number: X1226
• Description: Real Time Clock/Calendar with EEPROM
• Manufacturer: Xicor

X1226
Table 4. Programmable Frequency Output Bits
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 5. Digital Trimming Registers
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR0 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capaci-
tance adjustment. Using a Citizen CFS-206 crystal
with different ATR bit combinations provides an esti-
mated ppm range from +116ppm to -37ppm to the
nominal frequency compensation. The combination of
digital and analog trimming can give up to +146ppm
adjustment.
REV 1.1.24 1/13/03
FO1
DTR2
0
0
1
1
0
0
0
0
1
1
1
1
DTR Register
FO0
0
1
0
1
DTR1
0
1
0
1
0
1
0
1
(average of 100 samples)
DTR0
0
0
1
1
0
0
1
1
Output Frequency
Alarm IRQ output
32.768kHz
Estimated frequency
4096Hz
1Hz
PPM
+10
+20
+30
-10
-20
-30
0
0
www.xicor.com
The on-chip capacitance can be calculated as follows:
C
Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
See Application Section and Xicor’s Application Note
AN154 for more information.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/
control register requires the following steps:
– Write a 02h to the Status Register to set the Write
– Write a 06h to the Status Register to set both the
– Write one to 8 bytes to the Clock/Control Registers
– Writing all zeros to the status register resets both the
– A read operation occurring between any of the previ-
ATR
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write cycle,
so the sequence must be repeated to again initiate
another change to the CCR contents. If the
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
WEL and RWEL bits.
ous operations will not interrupt the register write
operation.
= [(ATR value, decimal) x 0.25pF] + 11.0pF
Characteristics subject to change without notice.
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