ADV7160 Analog Devices, ADV7160 Datasheet - Page 24

• Manufacturer Part Number: ADV7160
• Description: 96-Bit/ 220 MHz True-Color Video RAM-DAC
• Manufacturer: Analog Devices

ADV7160/ADV7162
Power-On Reset
On power-up, the ADV7160/ADV7162 executes a power-on re-
set operation. This initializes the pixel port such that the pixel
sequence ABCD starts at A. The Mode Register (MR17–MR10),
Command Register 2 (CR27–CR20), Command Register 3
(CR37–CR30) have all bits set to a Logic “1” and Address Reg-
ister, Command Register 1 (CR17–CR10), Command Register 4
(CR47–CR40) and Command Register 5 (CR57–CR50) have
all bits set to a Logic “0.”
The output clocking signals are also set during this reset period.
The power-on reset is activated when V
This reset is active for 1 s. The ADV7160/ADV7162 should
not be accessed during this reset period. The pixel clock should
be applied at power-up.
Color Palette Accesses
The Color Palette consists of 256 RAM locations, each location
containing 30 bits of color information. Data is written to the
color palette by firstly writing to the address register of the color
palette location to be modified. The MPU performs three suc-
cessive write cycles for each of the red, green and blue registers
(10-bit or 8-bit). Figures 35 to 38 illustrate write operations for
a 10-bit databus using the DACs in 8-bit and 10-bit mode and
write operations for an 8-bit databus using the DACs in 8-bit
and 10-bit mode. An internal pointer moves from red to green
to blue after each write is completed. This pointer is reset to
red after a blue write or whenever the address register is written.
During the blue write cycle, the three bytes of red, green and
Databus
Databus
Databus
Databus
Palette
Palette
Palette
Palette
PRGCKOUT = CLOCK/32
LOADOUT
R9
R9
R9
R9
R8
R8
R8
R8
D7
D7
D7
x
R7
R7
R7
R7
D6
D6
D6
x
Second Write Operation
Second Read Operation
First Write Operation
First Read Operation
R6
R6
R6
R6
= CLOCK/4:
D5
D5
D5
x
R5
R5
R5
R5
D4
D4
D4
x
AA
R4
R4
R4
R4
goes from 0 V to 5 V
D3
D3
D3
Figure 35. 8-Bit Data Bus Using 10-Bit DACs
x
R3
R3
R3
R3
D2
D2
D2
x
R2
R2
R2
R2
D1
D1
D1
D1
R1
R1
R1
R1
D0
D0
D0
D0
R0
R0
R0
R0
–24–
R/W
0
0
0
0
0
0
0
0
0
R/W
0
0
1
1
1
1
1
1
1
blue are concatenated into a single 30-bit/24-bit word and writ-
ten to the RAM location as specified in the address register
(A10–A0).
The address register then automatically increments to point to
the next RAM location and a similar red, green and blue palette
write sequence is performed. The address register resets to
000H following a blue write cycle to color palette RAM location
0FFH. The three color overlay palette is located in address
space above the main color palette. To access the Overlay
Palette, the Address Register must first be written with address
101H. From then on, the colors are accessed in the same way
as the main Color Palette, with the Address Register incrementing
after each blue access.
Data is read from the Color Palette by firstly writing to the ad-
dress register of the color palette location to be read. The MPU
performs three successive read cycles from each of the red,
green and blue locations (10-bit or 8-bit) of the RAM. Figures
35 to 38 illustrate read operations for a 10-bit databus using the
DACs in 8-bit and 10-bit mode and read operations for an 8-bit
databus using the DACs in 8-bit and 10-bit mode. An internal
pointer moves from red to green to blue after each read is com-
pleted. This pointer is reset to red after a blue read or whenever
the address register is written. The address register then auto-
matically increments to point to the next RAM location and a
similar red, green and blue palette read sequence is performed.
The address register resets to 000H following a blue read cycle
of color palette RAM location 0FFH. Similarly for the Overlay
Palette, the Address Register must first be written with address
101H. From then on, the colors are read in the same way as the
main Color Palette, with the Address Register incrementing af-
ter each blue access.
C1
0
0
0
0
0
0
0
0
0
C1
0
0
0
0
0
0
0
0
0
C0
0
0
1
1
1
1
1
1
1
.
.
C0
0
0
1
1
1
1
1
1
1
.
.
Palette Write
Write to Address Register (Lo- Byte)
Write to Address Register (Hi- Byte)
Write Red Data (R9–R2)
Write Red Data (R1–R0)
Write Green Data (G9–G2)
Write Green Data (G1–G0)
Write Blue Data (B9–B2)
Write Blue Data (B1–B0)
Write Red Data (R9–R2)
Palette Read
Write to Address Register (Lo- Byte)
Write to Address Register (Hi- Byte)
Read Red Data (R9–R2)
Read Red Data (R1–R0)
Read Green Data (G9–G2)
Read Green Data (G1–G0)
Read Blue Data (B9–B2)
Read Blue Data (B1–B0)
Read Red Data (R9–R2)
REV. 0