ADMC328 Analog Devices, ADMC328 Datasheet
ADMC328
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ADMC328 Summary of contents
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... TIMER One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 28-Lead ROM-Based ADMC328 150 Hz Minimum Switching Frequency Double/Single Duty Cycle Update Mode Control Programmable PWM Pulsewidth Special Crossover Function for Brushless DC Motors Individual Enable and Disable for Each PWM Output ...
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... Parameter Programming Resolution 2 Default Current Tuned Current NOTES 1 For ADC Calibration 3.5 V ICONST Voltage. Specifications subject to change without notice 5%, GND = +125 C for ADMC328T, CLKIN = 10 MHz, unless otherwise noted) Min Typ Max 0.3 3.5 –0 –20 0 +20 2 ...
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... Max Unit 2.40 2.50 2.60 V 2.45 2.50 2. ppm/ C Min Typ Max Unit –5.7 –5.1 –4.7 –280 155 190 mV –0.64 –0.53 –0.45 V Min Typ Max Unit 3.2 3.7 4.2 V 100 mV 1 3.2 ms –3– ADMC328 Conditions/Comments + +125 C SOIC A Conditions/Comments V = –0 0 –0 – 1 Conditions/Comments ...
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... ADMC328 TIMING PARAMETERS Parameter Clock Signals Signal t is defined as 0 The ADMC328 uses an input clock with a CK CKIN frequency equal to half the instruction rate MHz input clock (which is equivalent to 100 ns) yields processor cycle (equivalent to 20 MHz). When t values are within the range of 0.5 t ...
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... FRAME DELAY 0 [MFD = 0]) REV. B OUT SCS SCH SCDV t t SCDH SCDE t TDE t TDV t RDV Figure 2. Serial Port Timing –5– ADMC328 Min Max 100 0. SCK t SCP t SCP t SCDD ...
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... DD Input Voltage . . . . . . . . . . . . . . . . . . . . . –0 Output Voltage Swing . . . . . . . . . . . . . . –0 Operating Temperature Range (Ambient) ADMC328Y . . . . . . . . . . . . . . . . . . . . . . – +105 C ADMC328T . . . . . . . . . . . . . . . . . . . . . . – +125 C Storage Temperature Range . . . . . . . . . . . . – +150 C Lead Temperature (5 sec 280 C *Stresses greater than those listed may cause permanent damage to the device. ...
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... PWM signals with minimal processor overhead. The ADMC328 also contains two auxiliary PWM outputs, and nine lines of digital I/O. Because the ADMC328 has a limited number of pins, a number of functions such as the auxiliary PWM and the serial commu- nication port are multiplexed with the nine programmable input/ output (PIO) pins ...
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... When it reads data (not instructions) from 24-bit pro- gram memory to a 16-bit data register, the lower eight bits are placed in the PX register. The ADMC328 can respond to a number of distinct DSP core and peripheral interrupts. The DSP interrupts comprise a serial port receive interrupt, a serial port transmit interrupt, a timer interrupt, and two software interrupts ...
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... DR1 port of the SPORT1. The particular data receive pin selected is deter- mined by a bit in the MODECTRL register. PIN FUNCTION DESCRIPTION The ADMC328 is available in a 28-lead SOIC package and a 28-lead PDIP package. Table I describes the pins. Table I. Pin List Group ...
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... For proper operation of the ADMC328 this register must be set to 0x8000. The configuration of both the SYSCNTL and MEMWAIT registers of the ADMC328 are shown at the end of this data sheet. THREE-PHASE PWM CONTROLLER Overview The PWM generator block of the ADMC328 is a flexible, pro- ...
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... PWMSYNC pulse is produced at the mid- point of each PWM period. The width of the PWMSYNC pulse is programmable through the PWMSYNCWT register. The PWM signals produced by the ADMC328 can be shut off in a number of different ways. First, there is a dedicated asyn- chronous PWM shutdown pin, PWMTRIP, which, when brought LO, instantaneously places all six PWM outputs in the OFF state ...
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... ADMC328 Three-Phase Timing Unit The 16-bit three-phase timing unit is the core of the PWM con- troller and produces three pairs of pulsewidth modulated signals with high resolution and minimal processor overhead. There are four main configuration registers (PWMTM, PWMDT, PWMPD and PWMSYNCWT) that determine the fundamental charac- teristics of the PWM outputs ...
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... AL – PWMCHA where the subscript 1 refers to the value of that register during the first half cycle and the subscript 2 refers to the value during PWMTM the second half cycle. The corresponding duty cycles are: –13– ADMC328 PWMCHA – PWMDT ) t CK PWMTM – ...
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... ADMC328 PWMCHA PWMCHA 1 PWMTM PWMTM 1 PWMDT PWMDT 1 – PWMTM PWMTM PWMTM PWMTM 1 PWMTM PWMTM 1 PWCHA PWMDT 2 PWMTM PWMTM 1 because for the completely general case in double update mode, the switching period is given by (PWMTM + PWMTM S 1 Again, the values of T ...
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... PWM Shutdown In the event of external fault conditions essential that the PWM system be instantaneously shut down. Two methods of sensing a fault condition are provided by the ADMC328. For the first method, a low level on the PWMTRIP pin initiates an instantaneous, asynchronous (independent of DSP clock) shut- down of the PWM controller ...
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... The parameters of the 16-bit PWM Timer is tabulated in Table V. ADC OVERVIEW The ADC of the ADMC328 is based upon the single slope conversion technique. This approach offers an inherently monotonic conversion process and, to within the noise and sta- bility of its components, there will be no missing codes. ...
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... Figure 13 to ensure complete resetting. In order to compensate for IC process manufacturing tolerances (and to adjust for capacitor tolerances), the current source of the ADMC328 is software programmable. The software setting of the magnitude of the ICONST current generator is accomplished by selecting one of eight steps over an approximately 20% cur- rent range ...
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... ADMC328 Programmable Current Source The ADMC328 has an internal current source that is used to charge an external capacitor, generating the voltage ramp used for conversion. The magnitude of the output of the current source circuit is subject to manufacturing variations and can vary from one device to the next. Therefore, the ADMC328 incudes a pro- grammable current source whose output can always be tuned to within 5% of the target 100 A ...
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... Alternatively, by addition of a suitable filter network, the auxiliary PWM output signals can be used as simple single- bit digital-to-analog converters. The auxiliary PWM system of the ADMC328 can operate in two different modes: independent mode, or offset mode. The operating mode of the auxiliary PWM system is controlled by Bit 8 of the MODECTRL register ...
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... DSP core and motor control peripheral reset is performed. In addition, Bit 1 of the SYSSTAT register is set so that after a watchdog reset, the ADMC328 can determine that the reset was due to the timeout of the watchdog timer and not an external reset. Following a watchdog reset, Bit 1 of the SYSSTAT register may be cleared by writing zero to the WDTIMER register ...
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... Setting Bit 4 of the ICNTL register enables interrupt nesting. Interrupt Operation Following a reset, the ROM code on the ADMC328 must copy a default interrupt vector table into program memory RAM from address 0x0000 to 0x002F. Since each interrupt source has a dedicated four-word space in this vector table pos- sible to code short interrupt service routines (ISRs) in place ...
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... ADMC328 SYSTEM CONTROLLER The system controller block of the ADMC328 performs the fol- lowing functions: 1. Manages the interface and data transfer between the DSP core and the motor control peripherals. 2. Handles interrupts generated by the motor control periph- erals and generates a DSP core interrupt signal IRQ2. ...
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... ADMC328 SENSE Function System Control Register Memory Wait State Control Register Interval Timer Period Register Interval Timer Count Register Interval Timer Scale Register Reserved SPORT1 Control Register SPORT1 Clock Divide Register ...
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... ADMC328 CHANNEL CROSSOVER CROSSOVER B CHANNEL CROSSOVER 1 = CROSSOVER C CHANNEL CROSSOVER Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown. ...
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... PWMCHB (R/ PWMCHC (R/ –25– ADMC328 (0x200A) PWMPD PWMPD = T SECONDS MIN f CLKOUT (0x200B GDCLK GATE DRIVE CHOPPING FREQUENCY f CLKOUT f = CHOP 4 (GDCLK + 1) 2 ...
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... ADMC328 Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... PIO0 – PIO7 PIOFLAG1 ( PIO8 –27– ADMC328 (0x2006 INTERRUPT DISABLE 1 = INTERRUPT ENABLE (0x2046 INTERRUPT DISABLE 1 = INTERRUPT ENABLE (0x2007) ...
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... ADMC328 Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown. ...
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... ICONST_TRIM (R/ ICONST MIN = BITS 0 – 2 CLEARED. ICONST MAX = BITS 0 – 2 SET. –29– ADMC328 (0x2000 (0x2001 (0x2002 (0x2003) ...
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... ADMC328 OFFSET MODE AUXILIARY 1 = INDEPENDENT MODE PWM SELECT ADC 0 = CLKIN RATE COUNTER 1 = CLKOUT RATE SELECT 1ST HALF OF PWM CYCLE 1 = 2ND HALF OF PWM CYCLE Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... IMASK (R/ –31– ADMC328 0 = LEVEL 1 = EDGE DSP REGISTER INTERRUPT CLEAR TIMER SPORT1 RECEIVE OR IRQ0 SPORT1 TRANSMIT OR IRQ1 SOFTWARE 0 SOFTWARE 1 IRQ2 DSP REGISTER TIMER SPORT1 RECEIVE ...
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... ADMC328 0 = DISABLED SPORT1 ENABLE 1 = ENABLED Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field. PIN 1 0.250 (6.35) MAX 0.200 (5.05) 0.125 (3.18) 0.0118 (0.30) 0.0040 (0.10) SYSCNTL (R/ ...