MC6800 Motorola, MC6800 Datasheet
MC6800
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MC6800 Summary of contents
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... M6800 system parts, requires only one + 5.O-volt power supply, and no external TTL devices for bus interface. The MC6800 is capable of addressing 64K bytes of memory with its 16-bit address lines. The 8-bit data bus is bidirectional as well as three- state, making direct memory addressing and multiprocessing tions realizable ...
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... VCC= Min) (lLoad= – 100KA, VCC= Min) Output Low Voltage (lLoad = 1.6 mA, VCC = Min) Internal Power Dissipation (Measured TL) Capacitance (Vin=O, TA=250C, f=l.O MHz) — (M) MOTOROLA inputs voltages or electrical fields; however ad- I vised that normal precautions -40to + avoid application l-55to +150 I “ ...
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CLOCK TIMING (Vcc= 5,0 V, *5%, VSS=O, Characteristic Frequency of Operation Cycle Time (Figure 1) Clock Pulse Width (Measured at VCC– 0.6 V) Total 01 and 42 Up Time Rise and Fall Time (Measured between VSS +0.4 and VCC– O.6) ...
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... FIGURE 2 – READ DATA FROM MEMORY OR PERIPHERALS / ‘VIHC @l ~ Data Not Valid ~ ‘):., Data From MPU Data Not Valid k\\\\\\Y NOTES: 1. Voltage levels shown are VLSO.4, 2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise noted MOTOROLA @ Cycle Start of 0.4 v Start of Cvcle 2.4 V 0.4 v ktDDw+ VH> 2.4 V, unless otherwise specified Semiconductor Produck Inc. — ...
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... Vcc = 5.0v 1A= 25°C ~ 400 = 300 > ‘ : 200 / - ~ / 100 CL 0’ 0 100 200 300 CL, LOAO CAPACITANCE MOTOROLA @ FIGURE 5 – TYPICAL OUTPUT DELAY 600 lo H=-145*max@2.4V ‘lo L=l.6mAmax@0.4v -VCC=5.OV 500 25° 400 300 ~ ~ u 0 200 100 includes stray capacitance o 400 ...
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... Interrupt 6 a HALT 2 Instruction Decode Interrupt Request 4 39 Three-State Control Control 3 36+ Data Bus Enable Bus Available Valid Memory Address 34+ Read/Wtite, Rl~ Instruction MOTOROLA @ FIGURE 7 – =PANDED BLOCK DIAGRAM A13 A12 All A1O A9 A8 and 1 Register ..l.t\,, ‘*” Semiconductor ...
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... If TSC is in the high state, Bus Available Read/Write (R/~) – This TTL compatible the peripherals and memory devices wether MOTOROLA @ MPU SIGNAL DESCRIPTION that certain control Read (high) or Wrile specific func- this signal is Read (high). to determine turn Read/Write ...
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... This is done by insuring that no transitions of 41 (or 42) occur during this period. (Logic levels of the clacks are irrele- vant so long as they do not change). Since the MPU is a dynamic device, the 01 clock can be stopped for a maximum MOTOROLA @ time PW@H without then can be used in a short Direct Memory Access (DMA) application. ...
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... Address Bus, Data + MOTOROLA Iinesare back on the bus. Asingle to step through do this, HALT must such as LSRisused cle, the instruction returns high at tBA on the last cycle of the instruction the transitions of ...
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I Cycle Address Instruction Bus R/R VMA Interrupt IRQ Data Bus x Wait Pc 0-7 PC 8-15 I 0-7 I nst BA Note: ...
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... Negative (N), Zero (Z), Overflow (V), Carry from bit 7 (C), and half carry from bit 3 (H). These bits of the Condition Code Register are used as testable conditions for the condi- tional branch instructions. Bit 4 is the interrupt mask bit (l). The unused bits of the Condition Code Register (b6 and b7) are ones. MOTOROLA @ \ { :.~~> ...
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... EX1 3E WAI 7E JMP 7F CLR EX1 3F Swl m MOTOROLA MPU INSTRUCTION SET When an instruction code, the second byte, or the second and third bytes con- tain(s) an operand, an address, or information address is obtained during execution. Microprocessor load, store, general classifications: and stack because they operate on specific ...
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... Of memow location pointed to be Stack Pointer: Boolean Inclusive OR; Boolean Exclusive OR; & M Complement Transfer Into; o Bit = Zero; 00 Byte = Zero; Note – Accumulator addresbng mode instructions are included in tho column for IMPLIEO MOTOROLA @ - . . . . . .. .. ---- . . .. . .. . . . . .. ---- Z — ALUUMULAIUR AND MtMUMY UrErnAt BOOLEAN/ARITHMETIC AOORESSING MOOES EXTNO ...
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... N) Test: Result Iesstha” zero? (Bit MOTOROLA @ PROGRAM CONTROL OPERATIONS into two Stack Pointer is automatically (2) to the data transfer so that it will point to the last byte stack- ed rather than the next empty location. Note that the PULL instruction does not “remove” ...
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... I FIGURE 15 – STACK OPERATION, PUSH INSTRUCTION SP~m m+l 7F Previously 63 m+2 Stacked Data m+3 FD .{EI ‘c-- (a) Before Pc ~ PULA Next (a) Before m MOTOROLA ~’q..i, PSHA % SP+m+l Previously Stacked Data In$tr. PULA Semiconductor 16 MPU m (b) Aftar PSHA MPU ACCA m—2 m— mt2 \ m (b) After PULA Products Inc. ...
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... Branch to Subroutine and Jump to a~w~’tine (extended) instruction cept for th@~~n~&>The BS R instruction requires less opcode than J $$&R{%Q~#es versus 3 bytes) and also executes one cy - FIGURE 17 – PROGRAM FLOW FOR [X+K ~ MOTOROLA m — — T — — — ...
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... I “ Next * K = Signed (a) Before FIGURE 19 – PROGRAM FLOW FOR JSR (~TENDEm,\ n+ (a) Before Ex%utton ““s= (S formed from SH and SL) MOTOROLA FIGURE 18 – PROGRAM FLOW FOR BSR SP~m–2 m—1 m+l = Offset* I Main l“str. I 7-Bit value Execution , ~i)::~’ \ ,\~.,, ‘%, FIGURE 20 – PROGRAM FLOW FOR JSR (lNDWED) m— ...
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... SH = Subr. Addr. nt2 SL = Subr. Addr. nt3 I B Last Subr. Instr s“ Last Inter. I nstr. Pc — RTI (a) Before Execution MOTOROLA @ m—2 m—1 n+l n+2 FLOW FOR RTI m—7 CCR m—6 ACCB m—5 m—4 ACCA x~ m—3 XL m—2 m—1 PCH sp~ PCL ...
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... FFF9 Interrupt Memorv Assignment FFF8 I IRQ FFF9 IRQ FFFA Swl Swl FFFB NOTE: MS= Most Significant Address Bvte Least S~nificant Address Byte; MOTOROLA @ FIGURE ~ – PROGRAM FLOW FOR INTERRUPTS Wait For Hardware Interrupt or Interrupt NonMaskable Interrupt (NMI) Main Program Main Program m— ...
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... The instr~~lia~% shown in Table 5 are available for dire~#~@@@ulation of the CCR. A C~,$A/ instruction sequence operated earl~:~~$~~ processors, only if the preceding was $~d (Least Significant Bit= 1), Similarly MOTOROLA @ for testing relative are regarded as unsigned Z=l ; are in the range 00 (lowest) Z=4 ; comparison (CMP) value in the accumulator C=$ ...
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... MPU to obtain its instructions The programmer must have a method MPU’S internal registers and all of the external tions. Selection of the desired addressing user as the source statements are written. MOTOROLA @ = BOOLEAN OPERATION E 1 O+c 1 0+1 1 O+v 1 l+C 1 1+1 1 l-v A+CCR ...
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... Oprnd Two-Bvte Oprnd) ntl ZH n Oprnd n One-Bvte Oprnd) z& Two-Bvte OPrnd) [ MOTOROLA @ “operands” but the space between and Extended may be omitted. otherwise. There parent four character The addition instructions, the dual addressing mode even if Operator Operand modes are ADDA ...
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Comment Operator TSTB TEST CONTENTS OF ACCB or TSTA TEST CONTENTS OF ACCA A number of the instructions either alone or together an accumulator operand contain all of the address tion that is required, that is, ...
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Relative Address Mode – In both the Direct and Extended nodes, the address obtained by the MPU is an absolute ~umerical address. The Relative addressing )Iemented for the MPU’S branch instructions, nemory location relative to the Program Counter’s current Dcation. ...
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... The operand field can also contain a numetical will be automatically added to X during execution. mat is illustrated in Figure 33. When the MPU encounters the LDAB (Indexed) MOTOROLA @ INHERENT MOOE CYCLE-BY-CYCLE OPERATION VMA Line Address Bus 1 Op Code Address 1 Op Code Address + 1 Stack Pointer ...
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... STS STX Note 1. If device which is address during this cvcle uses VMA, Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus. B MOTOROLA FIGURE 30 – MODE MPU RAM m DATA ADOR * II PROGRAM MEMORY ‘C’* ?!i<,,l>; ...
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... CLR ROL COM ROR 6 DEC TST INC ~ device which IS addressed during Depending on bus capacitance, Note 2. For TST, VMA = O and Operand MOTOROLA @ FIGURE 31 – EXTENDED ADDRESSING MPU MPu R RAM RAM DATA ADDR = 300 PROGRAM PROGRAM w MEMORY MEMORY % PC = 5006 INSTR LDA Pc ADDR ...
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... Note 1. If device which is addressed during this cycle uses Depending on bus capacitance, data from the previous cycle may be retained on the Oata Bus. MOTOROLA @ a MODE MPU ~ Program i Memorv 5008 BEQ 15 Pc 5010 Next Instr. ...
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... Note 1. If device which is addressed during this cycle uses VMA, Oepending on bus capacitance, Note 2. For TST, VMA = O and Operand — MOTOROLA @ TABLE 11 – INDEXEO MOOE CYCLE-BY-CYCLE VMA Line Address Bus 1 Op Code Address 1 OP Code Address + 1 0 ...
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... Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume any Iiabilityarising out of the application or usa of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ...
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... I M070ROLA @ *,1,,,-, ,-84 PR,m,, ,. “,. 1.,,,,0 —-. — Semiconductor Products Inc. 3501 ED BLUESTEIN BLVD AUSTIN, TEXAS 78721 .20206 1s,000 LI,,m ——.——— A SUBSIDIARY OF MOTOROLA lNC — ,,,,7,12 —. —-. —. ———- — ...