MC6800 Motorola, MC6800 Datasheet - Page 17

• Manufacturer Part Number: MC6800
• Description: 8-BIT MICROPROCESSING UNIT (MPU)
• Manufacturer: Motorola

When
it adds the offset to the value in the Index Register and %,
the result as the address
ecuted.
tions
Always (BRA) instruction
bytes of the branch
cremented
and Jump to a~w~’tine
cept for th@~~n~&>The BS R instruction requires less opcode
than J $$&R{%Q~#es versus 3 bytes) and also executes one cy -
Always,
next instruction
struction
and the branch is limited to the rang~Wtkm$-
BRA instruction
but takes one more cycle to @?
(JSR)
18 through 20. Note t~%:$@Program
before it is stac~&i,;~~#~ration
The effect on program
Execution
Jump To Subroutine
IAI puts Address Bus, RN,
Branch If > Zero
Branch If >Zero
Branch If < Zero
Branch If Lower Or Same
Branch If Minus
Branch If Not Equal Zero
Branch If Overflow
Branch If Ovefilow
Branch If Plus
Branch To Subroutine
Jump
No Operation
Softwre
Wait for Interrupt%
OPERATIONS
Branch Always
Branch If Carry Clear
Branch If Carry Set
Branch If = Zero
Branch If Higher
Branch If < Zero
Return From Interrupt
Return From Subroutine
immediately
and Branch to
the MPU encounters
~
@
In the extended
—
BRA, affects program
Interrupt
except
(All)
(Bit 1) Set
to be$:~~~:n~
of the
to be executed
[X+K ~
Set
requires one les$by~
Clear
that the relative
following the JM P instructl~~~}K~WBranch
Load
Jump
instruction
Sw#rQu{*$ (BSR)
and
m
is required
when
addressing mode, the add[e~~~?he
Condition
(extended) instruction
is similar to the J~~?~#~&nded)
ita Businthet
fl~~ f$r the
MNEMONIC
of the next instruction
the Jump (Indexed)
Instruction,
interrupt
at the correct
FIGURE 17 – PROGRAM FLOW FOR
WAI
BRA
BCC
BEO
BGE
BGT
BLE
B LT
BMI
BNE
BVC
BVS
BPL
BSR
JMP
JSR
NOP
RTS
Swl
B CS
BHI
B LS
RTI
of the Branch to Subroutine
is fetched from
flow as shown in Figure 17.
MOTOROLA
to exit
~4,i. .‘.., ,..\. ?,,$< ‘
i~$~}%%.~~e opcode
Code
addre&Sin&. fiode
occurs.
Counter is properly in-
G
G
~
2C
2E
2F
20
2B
26
29
2A
80
24
25
27
22
23
28
than J M P (extended)
RE
the
Jump to Subroutine
Register
TABLE 4 – JUMP AND BRANCH INSTRUCTIONS
is shown
JMP,
hl
—
Y
—
‘n
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
wait
if
return
T —
T
~
#
2
2
2
2
2
2
2
2
2
2
2
z
2
2
2
previously
,$~$~*~~ca-
state.
(a) Jump
from
125 or + 127
and
is similar ex-
—
G —
AO
m
instruction,
6E
in Figures
to~b~;~x~$
address
Stack.
Branch
for the
applies
set,
in-
[ ,,-,
(See
a
low
Non-MaSk,:~e’’%?errUPt
~y :
i —
—
—
9
Special
17
3
Semiconductor
JUMP AND BRANCH INSTRUCTIONS
‘+~’$.. used as
—
—
# —
—
3
3
.*
the Wait for Interrupt,
hardware interrupts is shown in Figure 22. SW! causes the
address of the interrupt routine from the memory locations
that respond to the addresses FFFA and FFFB. Note that as
before being stacked. The Return from Interrupt instruction,
is, it can be used to stop operation
instruction
waits for the interrupt
stacking time from a hardware interrupt sequence,
gram as indicated in Figure 21,
M PU contents to be stacked and then fetches the starting
in the case of the subroutine
Counter is incremented to point at the correct return address
RTI, (Figure 22) is used at the end of an interrupt routine to
restore control to the main program. The SWI instruction
useful for inserting break points in the control program, that
registers in memory where they can be examined. The WAI
hardware interrupt;
Op$@tic
The effect of executing the Software Interrupt,
~+. ‘~
..?
L
I
I
I
I
I
the end of a subroutine
is used to decrease the time required to service a
Products Inc.
BRANCH
it stacks the MPU contents
(n+2)*Klxl
to occur, effectively
WAI, and their relationship
TEST
instructions,
to return to the main pro-
K = Signed 7-bit value
(b) Branch
and put the MPU
CONO. COOE REG.
removing
the Program
SWI, and
and then
T
Vc
10
to the
the
is