Z80182 Zilog., Z80182 Datasheet - Page 31

• Manufacturer Part Number: Z80182
• Description: Z8018x Family MPU
• Manufacturer: Zilog.

DS971820600
Zilog
Divide Ratio
SS, 2, 1, 0
General
000
001
010
011
100
101
110
111
Upon Reset
R/W
Bit
CNTLB0
MPBT
Invalid
R/W
(Divide Ratio = 10)
DR = 0 (x16)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
External Clock (Frequency < Ø
† /CTS - Depending on the condition of /CTS pin.
PS - Cleared to 0.
160
320
640
1280
2560
5120
10240
MP
R/W
PS = 0
0
Figure 11. ASCI Control Register B (Ch. 0)
/CTS/
R/W
PS
†
PE0
R/W
P R E L I M I N A R Y
0
DR
R/W
0
DR = 1 (x64)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
SS2
R/W
1
640
1280
2580
5120
10240
20480
40960
40)
SS1
R/W
1
Addr 02H
SS0
R/W
1
(Divide Ratio = 30)
DR = 0 (x16)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Clear To Send/Prescale
Multiprocessor
Multiprocessor Bit Transmit
480
960
1920
3840
7680
15360
30720
PS = 1
Z
ILOG
I
NTELLIGENT
DR = 1 (x64)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
Z80182/Z8L182
1920
3840
7680
15360
30720
61440
122880
P
ERIPHERAL
3-31