XC7336-10 Xilinx, XC7336-10 Datasheet - Page 2

• Manufacturer Part Number: XC7336-10
• Description: 36-Macrocell CMOS EPLD
• Manufacturer: Xilinx

XC7336 CMOS EPLD
Fast Function Blocks (FFB)
The XC7336 provides four Fast Function Blocks which
have 24 inputs that can be individually selected from the
UIM, 12 fast input pins, or the 9 Macrocell feedbacks from
the Function Block. The programmable AND array in each
Fast Function Block generates 45 product terms to drive
nine Macrocells in each FFB. Each Macrocell (Figure 2),
can be configured for registered or combinatorial logic.
Five product terms from the programmable AND array are
allocated to each Macrocell. Four of these product terms
are ORed together and may be optionally inverted before
driving the input of a programmable D-type flip-flop. The
fifth product term drives the asynchronous active-High
programmable Reset or Set Input to the Macrocell flip-
flop. The flip-flop can be configured as a D-type or Toggle
flip-flop or transparent for combinatorial outputs.
The programmable clock source is one of two global Fast-
CLK signals (FCLK0 or FCLK1) that are distributed with
short delay and minimal skew over the entire chip.
I/O Block
The Fast Function Block Macrocells drive chip outputs
directly through 3-state output buffers. Each output buffer
can be individually controlled by one of two dedicated
active-High Fast Output Enable inputs or permanently
Figure 2. Fast Function Block and Macrocell Schematic
12 from Fast
Input Pins
2 Global
Fast OE
Pin Feedback
Inputs from
Feedback
9 from FFB
to UIM
to UIM
UIM
Feedback
Macrocell
24
12
3
2
9
AND Array
P-Terms per
Macrocell
5 Private
5
Sum-of-Products
Macrocell
Previous
from
Succeeding Macrocell
Sum-of-Products to
2-24
enabled or disabled. The Macrocell output can also be
routed back as an input to the Fast Function Block, and
the UIM.
Power-On Characteristics/Master Reset
The XC7336 device undergoes a short internal initializa-
tion sequence upon device powerup. During this time (t
SET
configured from its internal EPROM array and all registers
are initialized. If the MR pin is tied to V
tion sequence is completely transparent to the user and is
completed in t
MR is held low while the device is powering up, the inter-
nal initialization sequence begins and outputs will remain
3-stated until the sequence is complete and MR is brought
High. V
tion sequence is performed correctly.
For additional flexibility, the MR pin is provided so the
EPLD can be reinitialized after power is applied. On the
falling edge of MR, all outputs become 3-stated and the
initialization sequence is started. The outputs will remain
3-stated until the internal initialization sequence is com-
plete and MR is brought High. The minimum MR pulse
width is t
before t
0
1
), the outputs remain 3-stated while the device is
Assignment
P-Term
Control
Output
Polarity
CC
RESET
WMR
Clocks
rise must be monotonic to insure the initializa-
Fast
0 1
, the outputs will become active after t
RESET
. If MR is brought High after t
1 of 9 Macrocells
Transparent
D/T
S/R
Register
Control
Q
after V
CCINT
has reached 4.75 V. If
OE Control
I/O Block
CCINT
, the initializa-
X5218
WMR
Pin
I/O
RESET
, but
RE-
.