MBM29F040C-55 FUJITSU [Fujitsu Component Limited.], MBM29F040C-55 Datasheet - Page 16

• Manufacturer Part Number: MBM29F040C-55
• Description: 4M (512K X 8) BIT
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

16
DQ
Toggle Bit I
DQ
Exceeded Timing Limits
DQ
Sector Erase Timer
MBM29F040C
The MBM29F040C also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
cause the DQ
See Figure 10 for the Toggle Bit timing specifications and diagrams.
DQ
these conditions DQ
cycle was not successfully completed. Data Polling DQ
this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in Table 2.
The DQ
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
DQ
used. If this occurs, reset the device with command sequence.
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command. DQ
be used to determine if the sector erase timer window is still open. If DQ
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
second status check, the command may not have been accepted.
Refer to Table 6: Hardware Sequence Flags.
6
5
3
5
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
6
to toggle.
5
will produce a “1”. This is a failure condition which indicates that the program or erase
3
6
prior to and following each subsequent sector erase command. If DQ
will stop toggling and valid data will be read on the next successive attempts. During
7
bit and DQ
6
-55/-70/-90
toggling between one and zero. Once the Embedded Program or Erase Algorithm
6
never stops toggling. Once the device has exceeded timing limits, the
6
to toggle. In addition, an Erase Suspend/Resume command will
7
, DQ
6
is the only operating function of the device under
3
3
is high (“1”) the internally controlled
is low (“0”), the device will accept
3
were high on the
3
may
3
will