MBM29F040C-55 FUJITSU [Fujitsu Component Limited.], MBM29F040C-55 Datasheet - Page 17

• Manufacturer Part Number: MBM29F040C-55
• Description: 4M (512K X 8) BIT
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

DQ
Toggle Bit II
Notes: 1. These status flags apply when outputs are read from a sector that has been erase-suspended.
Data Protection
Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Program
Erase
Erase Suspend Read
(Erase-Suspended Sector)
(Note 1)
Erase Suspend Program
This Toggle Bit II, along with DQ
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
address of the non-erase suspended sector will indicate a logic “1” at the DQ
DQ
Program operation is in progress. The behavior of these two status bits, along with that of DQ
as follows:
The MBM29F040C is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than 3.2 V (typically 3.7 V). If V
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored
until the V
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE = V
must be a logical zero while OE is a logical one.
2
2
6
2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
is different from DQ
CC
Write Inhibit
CC
Mode
level is greater than V
2
in that DQ
CC
6
< V
, can be used to determine whether the devices are in the Embedded Erase
LKO
LKO
6
.
toggles only when the standard program or Erase, or Erase Suspend
, the command register is disabled and all internal program/erase circuits
DQ
CC
7
DQ
DQ
(Note 2)
power-up and power-down, a write cycle is locked out for V
0
1
7
7
IL
, CE = V
2
to toggle during the Embedded Erase Algorithm. If the
IH
, or WE = V
MBM29F040C
toggles
toggles
toggles
DQ
1
IH
. To initiate a write cycle CE and WE
6
2
bit.
1 (Note 2)
7
, is summarized
toggles
toggles
-55/-70/-90
DQ
1
CC
2
power-up
CC
less
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