AD71028JST AD [Analog Devices], AD71028JST Datasheet
AD71028JST
Available stocks
Related parts for AD71028JST
AD71028JST Summary of contents
Page 1
FEATURES 2 complete independent BTSC encoders Pilot tone generator Includes subcarrier modulation Typical separation minimum Signal bandwidth of 14 kHz Phat-Stereo TM algorithm for stereo image enhancement Dialog enhancement function for playing wide ...
Page 2
AD71028 TABLE OF CONTENTS Specifications..................................................................................... 3 DAC Analog Performance........................................................... 3 BTSC Encoder Performance ....................................................... 3 Digital I/O ..................................................................................... 3 Power.............................................................................................. 4 Temperature Range ...................................................................... 4 Digital Timing............................................................................... 4 Absolute Maximum Ratings............................................................ 5 Pin Configuration and Functional Descriptions.......................... 6 Features .............................................................................................. ...
Page 3
SPECIFICATIONS TEST CONDITIONS, UNLESS OTHERWISE NOTED Supply Voltages ( Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Input Voltage HI Input Voltage LO DAC ANALOG PERFORMANCE Table 1. ...
Page 4
AD71028 POWER Table 4. Parameter Supplies Voltage, Analog and Digital Analog Current Digital Current Dissipation Operation—Both Supplies Operation—Analog Supplies Operation—Digital Supplies TEMPERATURE RANGE Table 5. Parameter Specifications Guaranteed Functionality Guaranteed Storage DIGITAL TIMING Table 6. Parameter t MCLK Recommended Duty ...
Page 5
ABSOLUTE MAXIMUM RATINGS Table 7. AD71028 Stress Ratings Parameter Min DV to DGND –0.3 DD ODV to DGND –0.3 DD AVDD to AGND –0.3 Digital Inputs DGND – 0.3 Analog Inputs AGND – 0.3 AGND to DGND –0.3 Reference Voltage ...
Page 6
AD71028 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Table 9. Pin Function Descriptions Pin No. Mnemonic 1 DIV2_PA 2 DIV1_PB 3 DIV2_PB 10, 26, 27 16, 44 DGND 7, 13, 17, 45 DVDD 8 ODVDD 11 ...
Page 7
Pin No. Mnemonic 40 CLK27_PA 41 CLK27_PB 42 PLL_PA 43 MCLK_PA 46 PLL_PB 47 MCLK_PB 48 DIV1_PA Input/Output Description IN Input for 27 MHz Video Reference Clock, Processor A IN Input for 27 MHz Video Reference Clock, Processor B IN ...
Page 8
AD71028 FEATURES The AD71028 is comprised of two independent digital-input BTSC encoders. The two processors allow two completely asynchronous BTSC channels to be encoded, each with its own clock signals. Figure 1 shows the block diagram of the device. Signal ...
Page 9
CLK27_PA, CLK27_PB Input pins to the divide-by-1125 block external PLL is used to generate the audio master clock, the 27 MHz video master clock may be applied to these pins where it is divided by 1125 to produce ...
Page 10
AD71028 SIGNAL PROCESSING L MATRIX R BACKGROUND OF BTSC BTSC is the name of the standard for adding stereo audio capability to the US television system many ways similar to the algorithm used for FM stereo broadcasts, ...
Page 11
PHASE LINEARITY OF THE EXTERNAL ANALOG FILTER If the time alignment of the pilot to the carrier signal is not close to 0 degrees, a loss of separation can occur. This means that the external analog low-pass filter should be ...
Page 12
AD71028 SPI PORT CLATCH CCLK CDATA CLATCH CCLK BYTE 0 CDATA HI-Z COUT OVERVIEW The AD71028 can be controlled using the SPI port. In general, there are three parameters per processor that can be controlled: the encoder output level, the ...
Page 13
PARAMETER RAM The parameters for the two BTSC processors are stored in two 256-location RAM spaces. The user should not change most of these parameters, although editing the dynamics processing curve for dialog enhancement may be useful if the curve ...
Page 14
AD71028 Table 13. SPI Control Register 1 Write format Byte 0 Byte 1 00000, Wb/R, Adr [9:8] Adr [7:0] Table 14. SPI Write Format for Parameter RAM, Output Level, Stereo Spreading and Dialog Enhancement Registers Byte 0 Byte1 000000, Adr ...
Page 15
LEFT CHANNEL LRCLK BCLK MSB SDATA LEFT CHANNEL LRCLK BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK SDATA MSB LRCLK BCLK MSB SDAT A NOTES 1. DSP mode does not identify the channel. 2. LRCLK normally operates ...
Page 16
AD71028 ANALOG OUTPUT SECTION Figure 11 shows the block diagram of the analog output section (one of two channels). A series of current sources is controlled by a digital Σ-∆ modulator. Depending on the digital code from the modulator, each ...
Page 17
... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range AD71028JST –0°C to +70°C AD71028JSTRL –0°C to +70°C 0.75 1.60 0.60 MAX 0.45 SEATING PLANE 10° 6° 0.20 2° 0.09 VIEW A 7° 3.5 ° 0° 0.08 MAX COPLANARITY VIEW A COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 13. 48-Lead Low Profile Quad Flatpack [LQFP] ...
Page 18
AD71028 NOTES Rev Page ...
Page 19
NOTES Rev Page AD71028 ...
Page 20
AD71028 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04482–0–1/04(0) Rev Page ...