AD71028JST AD [Analog Devices], AD71028JST Datasheet - Page 13

• Manufacturer Part Number: AD71028JST
• Description: Dual Digital BTSC Encoder with Integrated DAC
• Manufacturer: AD [Analog Devices]

PARAMETER RAM
The parameters for the two BTSC processors are stored in two
256-location RAM spaces. The user should not change most of
these parameters, although editing the dynamics processing
curve for dialog enhancement may be useful if the curve needs
to be changed for a specific application. This is explained in the
Dialog Enhancement Register section of this data sheet.
CONTROL REGISTER
Control Register 1 is an 11-bit register that controls serial
modes, de-emphasis, mute, power-down, and SPI-to-memory
transfers. Table 12 documents the contents of this register.
Bits 4:5 and 8:10 are reserved and should be set to 0 at all times.
The audio signal is muted with Bit 7 of the control register.
The soft power-down bit (Bit 6) stops the internal clocks to the
DSP core, but does not reset the part. The digital power con-
sumption is reduced to a low level when this bit is asserted.
Reset can only be asserted using the external reset pin.
Bits 3:2 select the serial format from one of four modes. These
different formats are discussed in the Initialization section of
this data sheet.
The word length bits (1:0) are used in right-justified serial
modes to determine where the MSB is located relative to the
start of the audio frame.
Table 12. Control Register Contents
Register Bits
10
9
8
7
6
5:4
3:2
1:0
Function
Reserved, Set to 0
Reserved, Set to 0
Reserved, Set to 0
Soft Mute (1 = Start Mute Sequence)
Soft Power-Down (1 = Power-Down)
Reserved, Set to 00
Serial In Mode
00 = I
01 = Right-Justified
10 = DSP
11 = Left-Justified
Word Length
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
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OUTPUT LEVEL REGISTER
The output level register controls the overall BTSC output level.
Its default value is –6 dB, which outputs a 600 mV rms reference
level for a 1 kHz 0 dB mono digital input signal. This value is in
2.20 format, and –6 dB corresponds to binary
0010000000000000000000. This register is used in conjunction
with the output filter to match the output BTSC level of the
encoder with the decoder input to achieve maximum separation
values. This level control should not be used to control the
overall volume level of the audio signal.
STEREO ENHANCEMENT REGISTER
This register controls ADI’s patented Phat Stereo spatial
enhancement algorithm. The default is all 0s, which corres-
ponds to no effect. The maximum setting is
0100000000000000000000, or a twos complement fractional
value of 1.0. Note that the bass energy in each channel is
increased using this algorithm, which may cause some digital
clipping on full-scale signal peaks, especially at low frequencies.
DIALOG ENHANCEMENT REGISTER
This controls the built-in dialog-enhancement algorithm, and
defaults to 0. The maximum setting is
0100000000000000000000, or a twos complement fractional
value of 1.0. This algorithm is intended to solve the problem of
playing back high dynamic range digital audio signals over a
television’s built-in speakers. It provides an amplitude boost to
signals that are in the range where dialog signals are usually
found, while at the same time preventing loud special effects
passages from overloading the speakers or amplifiers.
The dialog enhancement control is set up as a dynamics
processing curve with 33 locations on the curve, each spaced
3 dB apart. There is a default dialog enhancement curve that is
set at power-up, but this can be changed if a different curve is
desired. The curve ranges from an rms input level of –87 dB on
the low end to +9 dB on the high end. The value corresponding
to each point in the parameter RAM represents a gain at the
appropriate input level. This gain value should range from 0
(–∞ dB) to +2.0 – 1 LSB (approximately +6 dB). The gain at a
–87 dB input corresponds to parameter RAM location 4 on
Processor A and location 516 on Processor B. The table extends
to the +9 dB input gain at locations 36 and 548 for Processors A
and B, respectively.
AD71028