CY7C0241 CYPRESS [Cypress Semiconductor], CY7C0241 Datasheet - Page 10
![no-image](/images/no-image-200.jpg)
CY7C0241
Manufacturer Part Number
CY7C0241
Description
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY7C0241.pdf
(21 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C0241-15AC
Manufacturer:
CY
Quantity:
85
Part Number:
CY7C0241-15AC
Manufacturer:
CYP
Quantity:
20 000
Company:
Part Number:
CY7C0241-15AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C0241-15AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C0241-15AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
135
Company:
Part Number:
CY7C0241-15AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C0241-25AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
135
Company:
Part Number:
CY7C0241-25AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C0241-25AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C0241AV-20AC
Manufacturer:
CY
Quantity:
1 677
Company:
Part Number:
CY7C0241AV-25AC
Manufacturer:
CY
Quantity:
1
Document #: 38-06035 Rev. *C
Switching Characteristics
Data Retention Mode
The CY7C024/0241 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
Notes:
19. Test conditions used are Load 2.
20. t
21. CE = V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. Chip enable (CE) must be held HIGH during data retention,
2. CE must be kept between V
3. The RAM can begin operation >t
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
Busy Timing
Interrupt Timing
Semaphore Timing
Parameter
within V
during the power-up and power-down transitions.
minimum operating voltage (4.5V).
BDD
[20]
is a calculated parameter and is the greater of t
CC
, V
CC
in
= GND to V
to V
[19]
BUSY LOW from Address
Match
BUSY HIGH from Address
Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH
(Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE
or SEM)
SEM Flag Write to Read Time
SEM Flag Contention
Window
SEM Address Access Time
CC
[19]
– 0.2V.
CC
, T
Description
A
= 25°C. This parameter is guaranteed but not tested.
CC
– 0.2V and 70% of V
Over the Operating Range (continued)
RC
after V
WDD
CC
7C024/0241–15
7C025/0251–15
Min.
–
13
10
reaches the
5
0
5
5
t
PWE
(actual) or t
Note 20
CC
Max.
15
15
15
15
15
15
15
DDD
–
7C024/0241–25
7C025/0251–25
Min.
Timing
V
CE
ICC
t
20
12
10
10
SD
5
0
CC
(actual).
Parameter
DR1
[13]
Note 20
Max.
20
20
20
20
20
20
25
7C024/0241–35
7C025/0251–35
4.5V
Min.
@ VCC
30
15
10
10
Data Retention Mode
5
0
Test Conditions
V
CC
V
to V
CC
Note 20
DR
Max.
> 2.0V
CC
20
20
20
20
25
25
35
= 2V
– 0.2V
CY7C024/0241
CY7C025/0251
7C024/0241–55
7C025/0251–55
Min.
[21]
40
20
15
15
4.5V
5
0
Note 20
Max.
Page 10 of 21
1.5
Max.
45
40
40
35
30
30
55
V
t
IH
RC
Unit
mA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns