MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 33

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
COMMAND
NOTE: 1. DI b = data-in for column b.
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
2. An interrupted burst of 4 is shown; one data element is written.
3. t WTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last
four data elements.
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
WRITE to READ – Odd Number of Data, Interrupting
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
t
WTR
Figure 21
T2n
33
Bank a,
READ
Col n
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CL = 2
CL = 2
CL = 2
T4
NOP
DON’T CARE
128Mb: x4, x8, x16
T5
NOP
DI
DI
DI
n
n
n
DDR SDRAM
TRANSITIONING DATA
T5n
PRELIMINARY
©2001, Micron Technology, Inc.
T6
NOP
T6n