MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 53

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTES (continued)
39. The voltage levels used are derived from a
40. VIH overshoot: VIH(MAX) = V
41. V
42. This maximum value is derived from the
43 . For slew rates greater than 1V/ns the (LZ)
44 . During initialization, V
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
80
70
60
50
40
30
20
10
0
0.0
minimum V
In practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.
pulse width ≤ 3ns and the pulse width can not
be greater than 1/3 of the cycle rate. VIL
undershoot: VIL(MIN) = -1.5V for a pulse width ≤
3ns and the pulse width can not be greater than
1/3 of the cycle rate.
referenced test load. In practice, the values
obtained in a typical terminated design may
reflect up to 310ps less for
last DVW.
t
t
t
transition will start about 310ps earlier.
be equal to or less than V
tively, V
up, even if V
minimum of 42 ohms of series resistance is used
between the V
DQSCK(MAX) +
LZ(MIN) will prevail over
RPRE(MAX) condition.
DD
and V
TT
0.5
DDQ
t
may be 1.35V maximum during power
HZ(MAX) will prevail over
DD
DD
Pull-Down Characteristics
TT
/V
level and the referenced test load.
must track each other.
supply and the input pin.
DDQ
t
1.0
RPST(MAX) condition.
Figure C
V
are 0 volts, provided a
DDQ
OUT
DD
(V)
, V
t
t
HZ(MAX) and the
DQSCK(MIN) +
+ 0.3V. Alterna-
1.5
TT
, and V
DD
Q+1.5V for a
2.0
REF
must
2.5
53
45. The current Micron part operates below the
4 6.
47. For the -75 and -75Z, I
48. Random addressing changing 50% of data
49. Random addressing changing 100% of data
50. CKE must be active (high) during the entire time
51. IDD2N specifies the DQ, DQS, and DM to be
52. Whenever the operating frequency is altered, not
-100
-120
-20
-40
-60
-80
0
0.0
slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
t
35mA at 100 MHz.
changing at every transfer.
changing at every transfer.
a refresh command is executed. That is, from
the time the AUTO REFRESH command is
registered, CKE must be active at each rising clock
edge, until
driven to a valid high or low logic level. IDD2Q
is similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is “worst case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
RAP ≥
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD.
0.5
t
Pull-Up Characteristics
REF later.
Figure D
1.0
128Mb: x4, x8, x16
V
DD
Q - V
DD
OUT
3N is specified to be
(V)
1.5
DDR SDRAM
PRELIMINARY
©2001, Micron Technology, Inc.
2.0
2.5