MT48LC128M4A2_07 MICRON [Micron Technology], MT48LC128M4A2_07 Datasheet - Page 16

• Manufacturer Part Number: MT48LC128M4A2_07
• Description: 512Mb x4, x8, x16 SDRAM
• Manufacturer: MICRON [Micron Technology]

Figure 6:
Table 5:
Operating Mode
WRITE Burst Mode
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
CAS Latency
CAS Latency
latency is programmed to two clocks, the DQs will start driving after T1 and the data will
be valid by T2, as shown in Figure 6. Table 5 indicates the operating frequencies at which
each CL setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
COMMAND
COMMAND
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed burst length applies to READ bursts, but write accesses
are single-location (nonburst) accesses.
CLK
CLK
DQ
DQ
Speed
READ
READ
T0
-7E
-75
T0
NOP
NOP
T1
T1
CL = 2
t
t AC
CL = 3
LZ
16
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CL = 2
≤ 133
≤ 100
T3
T3
NOP
D
t OH
OUT
Allowable Operating
Frequency (MHz)
Don’t Care
Undefined
512Mb: x4, x8, x16 SDRAM
T4
©2000 Micron Technology, Inc. All rights reserved.
Register Definition
CL = 3
≤ 143
≤ 133