MT48LC128M4A2_07 MICRON [Micron Technology], MT48LC128M4A2_07 Datasheet - Page 54
MT48LC128M4A2_07
Manufacturer Part Number
MT48LC128M4A2_07
Description
512Mb x4, x8, x16 SDRAM
Manufacturer
MICRON [Micron Technology]
Datasheet
1.MT48LC128M4A2_07.pdf
(68 pages)
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Figure 38:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMU
COMMAND
BA0, BA1
A11, A12
A0–A9,
DQM/
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
READ – Without Auto Precharge
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
NOP
DISABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
T2
BANK
READ
t CH
t CMH
CAS Latency
T3
NOP
t LZ
t AC
54
T4
NOP
D
OUT
t OH
t AC
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
T5
OUT
NOP
m + 1
t OH
t AC
SINGLE BANK
PRECHARGE
ALL BANKS
D
BANK
T6
512Mb: x4, x8, x16 SDRAM
OUT
t OH
m + 2
t RP
t AC
©2000 Micron Technology, Inc. All rights reserved.
D
T7
NOP
OUT
t OH
m + 3
Timing Diagrams
t HZ
ROW
BANK
T8
ROW
ACTIVE
Don’t Care
Undefined
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