MT48LC128M4A2_07 MICRON [Micron Technology], MT48LC128M4A2_07 Datasheet - Page 39
![no-image](/images/no-image-200.jpg)
MT48LC128M4A2_07
Manufacturer Part Number
MT48LC128M4A2_07
Description
512Mb x4, x8, x16 SDRAM
Manufacturer
MICRON [Micron Technology]
Datasheet
1.MT48LC128M4A2_07.pdf
(68 pages)
- Current page: 39 of 68
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PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
11. Does not affect the state of the bank and acts as a NOP to that bank.
5. The following states must not be interrupted by any executable command; COMMAND
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
state for precharging.
less of bank.
auto precharge enabled and READs or WRITEs with auto precharge disabled.
Accessing mode
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
register:
t
state.
Starts with registration of a LOAD MODE REGISTER command and ends
when
all banks idle state.
t
RC is met. After
RP is met. After
t
MRD has been met. After
39
t
t
RC is met, the SDRAM will be in the all banks idle
RP is met, all banks will be in the idle state.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
MRD is met, the SDRAM will be in the
512Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
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