AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 31

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

Step 3 The next write of the processor hits the cache
Step 4 In the same clock cycle, a snoop request to the
Step 5 Two clock cycles after EADS asserts, HITM be-
Step 6 Because the processor-initiated access cannot
Step 7 During the write-back sequence, AHOLD is
Step 8 The write-back access is finished when BLAST
Step 9 After the last write-back access, the BIU starts
CLK
Write Buffer
Cached Data
AHOLD
EADS
HITM
ADS
BLAST
BRDY
Note:
The circled numbers in this figure represent the steps in section 4.8.7.1.
Data
and the line is non-shared. Therefore, data B is
written into the cache. The cache line transits
to the modified state.
same address where data B resides is started
because EADS = 0. The snoop hits a modified
line. EADS is ignored due to the hit of a modified
line, but is detected again as early as in step 10.
comes valid.
be finished (AHOLD is still 1), the BIU gives
priority to a write-back access that does not re-
quire the use of the address bus. Therefore, in
the clock cycle, the cache starts the write-back
sequence indicated by ADS = 0 and W/R = 0.
deasserted.
and BRDY transition to 0.
writing data A from the write buffers. This is
indicated by ADS = 0 and W/R = 0.
B original
XXX
1
2
Figure 14. Write Cycle Reordering Due to Buffering
A
3
B modified
4
Am5
X
PRELIMINARY
86 Microprocessor
5
6
Step 10 In the same clock cycle, the snooping cache
Step 11 The write of data A is finished if BRDY transi-
The software write sequence was first data A and then
data B. But on the external bus the data appear first as
data B and then data A. The order of writes is changed.
In most cases, it is unnecessary to strictly maintain the
ordering of writes. However, some cases (for example,
writing to hardware control registers) require writes to
be observed externally in the same order as pro-
grammed. There are two options to ensure serialization
of writes, both of which drive the cache to Write-through
mode:
1. Set the PWT bit in the page table entries.
2. Drive the WB/WT signal Low when accessing these
Option 1 is an operating-system-level solution not di-
rectly implemented by user-level code. Option 2, the
hardware solution, is implemented at the system level.
B
memory locations.
Ignored
drives HITM back to 1.
tions to 0 (BLAST = 0), because it is a single
word.
B+4
7
B+8
B+12
8
10
9
A
11
AMD
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