AM29LV800BB-120EC AMD (ADVANCED MICRO DEVICES), AM29LV800BB-120EC Datasheet
AM29LV800BB-120EC
Specifications of AM29LV800BB-120EC
Related parts for AM29LV800BB-120EC
AM29LV800BB-120EC Summary of contents
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Data Sheet This product has been retired and is not recommended for designs. For new and current designs, S29AL008D supersedes Am29LV800B and is the factory-recommended migration path. Please refer to the S29AL008D datasheet for specifications and ordering information. Availability of ...
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... Program and Erase Operation Status .................. 12 Standby Mode ...................................................... 12 Automatic Sleep Mode ......................................... 12 RESET#: Hardware Reset Pin ............................. 12 Output Disable Mode ............................................ 12 Table 2. Am29LV800BT Top Boot Block Sector Addresses ........................................................13 Table 3. Am29LV800BB Bottom Boot Block Sector Addresses ........................................................13 Autoselect Mode ................................................... 14 Table 4. Am29LV800B Autoselect Codes (High Voltage Method) ................................................14 Sector Protection/Unprotection ............................ 14 Temporary Sector Unprotect ................................ 14 Figure 1 ...
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6/1/ ...
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Am29LV800B 8 Megabit ( 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory For new designs, S29AL008D supersedes Am29LV800B and is the factory-recommended migration path for this device. Please refer to the S29AL008D Family Datasheet for ...
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GENERAL DESCRIPTION The Am29LV800B Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The device is also available in Known Good ...
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... Program and Erase Operation Status .................. 12 Standby Mode ...................................................... 12 Automatic Sleep Mode ......................................... 12 RESET#: Hardware Reset Pin ............................. 12 Output Disable Mode ............................................ 12 Table 2. Am29LV800BT Top Boot Block Sector Addresses ........................................................13 Table 3. Am29LV800BB Bottom Boot Block Sector Addresses ........................................................13 Autoselect Mode ................................................... 14 Table 4. Am29LV800B Autoselect Codes (High Voltage Method) ................................................14 Sector Protection/Unprotection ............................ 14 Temporary Sector Unprotect ................................ 14 Figure 1 ...
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PRODUCT SELECTOR GUIDE Family Part Number Speed Options Full Voltage Range: V Max access time ACC Max CE# access time Max OE# access time See “AC Characteristics” for full ...
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CONNECTION DIAGRAMS This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information. A15 1 A14 2 A13 3 A12 4 A11 5 A10 ...
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CONNECTION DIAGRAMS This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information. RY/BY# A18 A17 CE OE# ...
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Special Handling Instructions for FBGA Package Special handling is required for Flash Memory prod- ucts in FBGA packages. PIN CONFIGURATION A0–A18 = 19 addresses DQ0–DQ14= 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte ...
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... Bottom sector Valid Combinations for FBGA Packages Order Number AM29LV800BT-70, AM29LV800BB-70 AM29LV800BT-90, AM29LV800BB-90 AM29LV800BT-120, AM29LV800BB-120 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command reg- ister itself does not occupy any addressable memory location. The register is composed of ...
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The device features an Unlock Bypass mode to facil- itate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” ...
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... SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Table 3. Am29LV800BB Bottom Boot Block Sector Addresses Sector A18 A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 ...
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Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verifica- tion, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be pro- grammed with its ...
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START RESET (Note 1) Perform Erase or Program Operations RESET Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 1. Temporary ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 1 for command definitions). In addition, the following hardware data protection measures prevent acci- dental erasure or ...
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The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufac- turer code. A read cycle at ...
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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip ...
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See “Write Operation Status” for informa- tion on these status bits. After an erase-suspended program operation is com- plete, the system can once again read array data within ...
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Table 1. Am29LV800B Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 2 and the following subsec- tions describe the functions of these bits. DQ7, RY/BY#, and DQ6 ...
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If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend ...
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START Read DQ7–DQ0 (Note Read DQ7–DQ0 Toggle Bit = Toggle? Yes No DQ5 = 1? Yes Read DQ7–DQ0 Twice (Notes 1, 2) Toggle Bit = Toggle? Yes Program/Erase Operation Not Complete, Write Operation Complete Reset Command Notes: 1. Read toggle ...
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Operation Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Reading within Erase Suspended Sector Erase Suspend Reading within Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . .–65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . .–65°C ...
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DC CHARACTERISTICS CMOS Compatible Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I CC2 (Notes ...
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DC CHARACTERISTICS (Continued) Zero Power Flash 500 1000 Addresses are switching at 1 MHz Note: Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C L 6.2 kΩ Diodes are IN3064 or equivalent Note: Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V Input 1.5 V 0.0 V Table 3. Test Specifications ...
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AC CHARACTERISTICS Read Operations Parameter JEDEC Std t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output Delay ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write (See Note) t RESET# ...
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AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter JEDEC Std t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# BYTE# ...
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AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE Data RY/BY VCS Notes program address program data Illustration shows device ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY Notes sector address (for Sector Erase Valid ...
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AC CHARACTERISTICS t RC dresses VA t ACC OE# t OEH WE# DQ7 Q0–DQ6 t BUS RY/BY Valid address. Illustration shows first status cycle after command sequence, last status read cycle, ...
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AC CHARACTERISTICS Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an Note: erase-suspended sector. Temporary Sector ...
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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 μs CE# WE# OE# * For sector protect For sector unprotect ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH DS ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t R RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Mode Chip Programming Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following conditions: 25 programming typicals ...
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PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. 42 Dwg rev AA; 10/99 Am29LV800B ...
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PHYSICAL DIMENSIONS TSR048—48-Pin Reverse TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. Am29LV800B Dwg rev AA; 10/99 43 ...
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PHYSICAL DIMENSIONS FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA Am29LV800B Dwg rev AF; 10/99 ...
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PHYSICAL DIMENSIONS SO 044—44-Pin Small Outline Package 45 Am29LV800B Dwg rev AC; 10/99 ...
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REVISION SUMMARY Revision E (January 1998) Distinctive Characteristics Changed typical read and program/erase current specifications. Device now has a guaranteed minimum endurance of 1,000,000 write cycles. In-System Sector Protect/Unprotect Algorithm Figure Corrected Changed wait specification to 150 ...
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AC Characteristics—Figure 17. Program Operations Timing and Figure 18. Chip/Sector Erase Operations Deleted t and changed OE# waveform to start at GHWL high. Physical Dimensions Replaced figures with more detailed illustrations. Revision G+1 (July 7, 2000) Ordering Information Inserted dashes ...