AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 59

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

The AC specifications, provided in the AC characteris-
tics table, consist of output delays, input setup require-
ments, and input hold requirements. All AC specifica-
tions are relative to the rising edge of the CLK signal.
AC specifications measurement is defined by Figure 39.
All timings are referenced to 1.5 V unless otherwise
specified. Am5
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
33-MHz bus (133-MHz operating frequency)
V
Notes:
1. Specifications assume C
2. 0-MHz operation guaranteed during stop clock operation.
3. Not 100% tested. Guaranteed by design characterization.
4. For faster transitions (>0.1% between adjacent clocks), use the Stop Clock protocol to switch operating frequency.
5. All timings are referenced at 1.5 V (as illustrated in the listed figures) unless otherwise noted.
Symbol
CC
t
Order I/O buffer models for the processor are available.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
18a
= 3.3 V ±0.3 V; T
t
t
t
t
t
t
t
t
t
1a
8a
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
Frequency
CLK Period
CLK Period Stability
CLK High Time at 2 V
CLK Low Time at 0.8 V
CLK Fall Time (2 V–0.8 V)
CLK Rise Time (0.8 V–2 V)
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK, FERR, BREQ, HLDA,
SMIACT, HITM Valid Delay
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK Float Delay
PCHK Valid Delay
BLAST, PLOCK, Valid Delay
BLAST, PLOCK, Float Delay
D31–D0, DP3–DP0 Write Data Valid Delay
D31–D0, DP3–DP0 Write Data Float Delay
EADS, INV, WB/WT Setup Time
EADS, INV, WB/WT Hold Time
KEN, BS16, BS8 Setup Time
KEN, BS16, BS8 Hold Time
RDY, BRDY Setup Time
RDY, BRDY Hold Time
HOLD, AHOLD Setup Time
BOFF Setup Time
HOLD, AHOLD, BOFF Hold Time
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Setup Time
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Hold Time
D31–D0, DP3–DP0, A31–A4 Read Setup Time
D32–D0, DP3–DP0, A31–A4 Read Hold Time
X
86 microprocessor output delays are
CASE
L
= 0°C to + 85°C; C
= 50 pF. I/O Buffer model must be used to determine delays due to loading (trace and component). First
Parameter
Am5
L
= 50 pF unless otherwise specified
X
PRELIMINARY
86 Microprocessor
Preliminary Info
specified with minimum and maximum limits, measured
as shown. The minimum microprocessor delay times
are hold times provided to external circuitry. Input setup
and hold times are specified as minimums, defining the
smallest acceptable sampling window. Within the sam-
pling window, a synchronous input signal must be stable
for correct microprocessor operation.
Min
30
11
11
8
3
3
3
3
3
3
3
5
3
5
3
5
3
6
7
3
5
3
5
3
0.1%
Max
125
33
14
20
14
14
20
14
20
3
3
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
43, 44
43, 44
39
39
39
39
39
40
41
42
40
41
40
41
43
43
43
43
44
44
43
43
43
43
43
Note 2
Adjacent Clocks
Notes 3 and 4
Note 3
Note 3
Note 3
Note 3
Note 5
Note 3
Note 3
Note 3
Note 5
Note 5
Notes
AMD
59