CAT1025 CATALYST [Catalyst Semiconductor], CAT1025 Datasheet - Page 12
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CAT1025
Manufacturer Part Number
CAT1025
Description
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet
1.CAT1025.pdf
(20 pages)
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Acknowledge Polling
Figure 10. Immediate Address Read Timing
CAT1024, CAT1025
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write opration, the
CAT1024/25 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
WRITE PROTECTION
The Write Protection feature (CAT1025 only) allows the
user to protect against inadvertent memory array
programming. If the WP pin is tied to V
Doc. No. 3008, Rev. M
SDA
SCL
BUS ACTIVITY:
SDA LINE
MASTER
DATA OUT
8TH BIT
8
CC
S
S
A
R
T
T
, the entire
ADDRESS
SLAVE
12
memory array is protected and becomes read only. The
CAT1025 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Read Operations
The READ operation for the CAT1024/25 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
9
C
A
K
NO ACK
DATA
N
O
C
A
K
P
O
S
T
P
STOP