CAT1025 CATALYST [Catalyst Semiconductor], CAT1025 Datasheet - Page 6
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CAT1025
Manufacturer Part Number
CAT1025
Description
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet
1.CAT1025.pdf
(20 pages)
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RELIABILITY CHARACTERISTICS
AC TEST CONDITIONS
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage V
3. Power-Down, Input Reference Voltage V
4. V
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. t
7. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V
CAT1024, CAT1025
Doc. No. 3008, Rev. M
RESET CIRCUIT AC CHARACTERISTICS
P
Symbol
N
T
V
I
LTH
M
O
DR
ZAP
END
PUR
S
S
CC
R
W
y
t
y
t
(5)
(5)(7)
G
P
t
t
t
t
t
m
m
(5)
M
P
M
O
U
R
L
P
Glitch Reference Voltage = V
(5)
and t
G
T I
E
U
R
U
n I
n I
R
P
R
b
b
W
u
D
W
R
S
C
D
t i l
- R
p
p
T
H
p t
l o
l o
n I
h c
t u
t u
PUW
t u
p
U
t u
R
R
Endurance
Data Retention
ESD Susceptibility
Latch-Up
R
O
Parameter
P
P
s i
e
are the delays required from the time V
P
e
u
a
e f
e
M
I T
e f
u
p t
a r
e r
M
s l
a
R
V
e r
P
P
t u
M
V
m
n
e
n
C
a
o
o
I
d
n
T
C
c
p n
u n
t e
L
w
H
N I
w
V
c
e
G
F
o
e
r e
o t
r e
l o
r e
l a
t u
l l a
a
V
t i l
G
a t
V
U -
d
M
U -
l o
R
R
h c
R
o t
5
l o
g
i T
R
E
6 ,
a t
P
P
p
s e
p
s e
e
a t
m
S
R
R
a
a
g
P
s
o t
o t
THmin
t e
g
a r
t e
a r
E
E
e
e
e
l u
e
s
T
e j
S
s
R
W
m
T
m
s
CC
e s
G
E
t c
e
m i
O
; Based on characterization data
r
t e
t i l
t e
d a
T
e t i
= V
CC
u
W
P
h c
o e
r e
r e
MIL-STD-883, Test Method 1033 1,000,000
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
p t
O
l u
d i
= V
TH
O
O
t u
u
t u
e s
m I
h t
p
p
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
p t
TH
Reference Test Method
r e
r e
D
m
t u
W
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
JEDEC Standard 17
l e
i t a
i t a
n u
d i
D
y a
n o
n o
CC
y t i
l e
h t
C
y a
r u
is stable until the specified memory operation can be initiated.
e r
T
0
t n
e
0
C
C
2 .
C
t s
3 .
N
S
o
o
V
L
6
N
N
N
N
N
V
o
n
o
n
T
T
C
C
0
=
u
o
o
e t
1
d
o
o
o
d
C
C
e
e
5 .
C
e t
o
0
c r
e t
t i
e t
e t
e t
t i
o t
t s
t s
,
1
4
n
V
o i
o i
: e
n
0
0
5 ,
2
3
d
1
1
1
C
0
s
7 .
s n
s n
0
C
t i
8 .
p
I
V
o i
O
F
V
L
C
n
C
C
=
s
C
3
m
M
M
1
; A
0 3
5
n i
n i
2000
Min
100
100
CC
T
T
+ 1V.
2
p y
0 0
p y
Max
M
M
2
2
2
1
0 3
0 7
5
0 0
0 7
0 7
1
x a
x a
Cycles/Byte
Units
Years
Volts
mA
U
U
m
m
m
i n
s µ
s µ
s µ
i n
s n
s n
s
s
s
s t
s t