CY7C1470V25-167AXI CYPRESS [Cypress Semiconductor], CY7C1470V25-167AXI Datasheet - Page 14

• Manufacturer Part Number: CY7C1470V25-167AXI
• Description: 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05290 Rev. *I
Scan Register Sizes
Identification Codes
Instruction
Bypass
ID
Boundary Scan Order–165FBGA
Boundary Scan Order–209BGA
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Register Name
Code
000
001
010
011
100
101
110
111
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1-compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM opera-
tions.
Bit Size (x36)
32
71
3
1
–
Description
Bit Size (x18)
32
52
3
1
–
CY7C1470V25
CY7C1472V25
CY7C1474V25
Bit Size (x72)
Page 14 of 28
110
32
3
1
–
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