CY7C1470V25-167AXI CYPRESS [Cypress Semiconductor], CY7C1470V25-167AXI Datasheet - Page 9

• Manufacturer Part Number: CY7C1470V25-167AXI
• Description: 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05290 Rev. *I
Partial Write Cycle Description
Read
Write – No bytes written
Write Byte a – (DQ
Write Byte b – (DQ
Write Bytes b, a
Write Byte c – (DQ
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQ
Write Bytes d, a
Write Bytes d, b
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
Write All Bytes
Read
Write – No Bytes Written
Write Byte X − (DQ
Write All Bytes
Note:
8. Table only lists a partial listing of the Byte Write combinations. Any combination of BW
Read
Write – No Bytes Written
Write Byte a – (DQ
Write Byte b – (DQ
Write Both Bytes
active.
Function (CY7C1470V25)
c
a
b
d
x
a
b
and DQP
and DQP
and DQP
and DQP
and DQP
Function (CY7C1472V25)
Function (CY7C1474V25)
and DQP
and DQP
c
a
b
d
x)
)
)
)
a
b
)
)
)
[1, 2, 3, 8]
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
[a:d]
is valid. Appropriate Write will be done based on which Byte Write is
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
d
WE
H
L
L
L
L
WE
BW
H
L
L
L
LL
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
c
BW
H
H
x
L
L
b
CY7C1470V25
CY7C1472V25
CY7C1474V25
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
b
All BW = L
Page 9 of 28
BW
BW
H
H
H
L
L
L
x
x
BW
a
x
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
a
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