CY7C1480BV25-167AXI CYPRESS [Cypress Semiconductor], CY7C1480BV25-167AXI Datasheet - Page 9

• Manufacturer Part Number: CY7C1480BV25-167AXI
• Description: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE
appropriate combination of the write inputs (GW, BWE, and
BW
byte(s). ADSC-triggered write accesses need a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is
a common IO device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so tri-states the output drivers. As a safety precaution,
DQs are automatically tri-stated whenever a write cycle is
detected, regardless of the state of OE.
Burst Sequences
The
provides a two-bit wraparound counter, fed by A1: A0, that imple-
ments either an interleaved or linear burst sequence. The inter-
leaved burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed to
support processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
ZZ Mode Electrical Characteristics
Document #: 001-15143 Rev. *D
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
X
Parameter
) are asserted active to conduct a write to the desired
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
1
, CE
Sleep Mode Standby Current
Device Operation to ZZ
ZZ Recovery Time
ZZ Active to Sleep Current
ZZ Inactive to Exit Sleep Current
2
, CE
3
are all asserted active, and (4) the
Description
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Sleep Mode
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock cycles
are required to enter into or exit from this “sleep” mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the “sleep” mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the “sleep” mode. CE
ADSP, and ADSC must remain inactive for the duration of t
after the ZZ input returns LOW.
Table 2. Interleaved Burst Address Table
(MODE = Floating or V
Table 3. Linear Burst Address Table
(MODE = GND)
Address
Address
Test Conditions
DD
DD
A1: A0
A1: A0
First
First
00
01
10
00
01
10
11
11
– 0.2V
– 0.2V
CY7C1482BV25, CY7C1486BV25
Address
Address
Second
Second
A1: A0
A1: A0
01
00
10
01
10
00
11
11
DD
)
2t
Min
CYC
0
Address
Address
A1: A0
A1: A0
CY7C1480BV25
Third
Third
10
00
01
10
11
00
01
11
2t
2t
Max
120
CYC
CYC
1
Page 9 of 31
Address
Address
, CE
Fourth
A1: A0
Fourth
A1: A0
00
01
10
11
10
01
00
11
Unit
mA
2
ns
ns
ns
ns
, CE
ZZREC
3
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