W83194R-39A WINBOND [Winbond], W83194R-39A Datasheet - Page 17

• Manufacturer Part Number: W83194R-39A
• Description: 100MHZ 3-DIMM CLOCK
• Manufacturer: WINBOND [Winbond]

10.0 POWER MANAGEMENT TIMING
For synchronous Chipset, CPU_STOP# pin is an asynchronous “ active low ” input pin used to stop
the CPU clocks for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run
while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU “c locks on latency “ is less than 4 CPU clocks and
“c locks off latency ” is less then 4 CPU clocks.
10.2 PCI_STOP# Timing Diagram
For synchronous Chipset, PCI_STOP# pin is an asynchronous “a ctive low ” input pin used to stop
the PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run
while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume
output with full pulse width. In this case, PCI “c locks on latency “ is less than 2 PCI clocks and
“c locks off latency ” is less then 2 PCI clocks.
10.1 CPU_STOP# Timing Diagram
CPUCLK[0:3]
CPU_STOP#
PCICLK_F
CPUCLK
(Internal)
(Internal)
PCI_STOP#
PCICLK[0:5]
PCICLK
SDRAM
PCICLK_F
CPUCLK
(Internal)
(Internal)
PCICLK
1
2
3
1
4
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Publication Release Date: May 1998
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W83194R-39/-39A
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PRELIMINARY
Revision 0.20