CY7C342 CYPRESS [Cypress Semiconductor], CY7C342 Datasheet - Page 4

• Manufacturer Part Number: CY7C342
• Description: 128-Macrocell MAX EPLDs
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-03014 Rev. *B
Design Security
The CY7C342B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the entire
device.
The CY7C342B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
Typical I
400
300
200
100
100 Hz
0
CC
1 kHz
vs. f
V
Room Temp.
MAXIMUM FREQUENCY
CC
10 kHz
= 5.0V
MAX
100 kHz 1 MHz
10 MHz
USE ULTRA37000
50 MHz
ALL NEW DESIGNS
Output Drive Current
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t
additional t
compared to a signal from straight input pin.
When calculating synchronous frequencies, use t
inputs are on dedicated input pins. When expander logic is
used in the data path, add the appropriate maximum expander
delay, t
or 1/(t
frequencies is the maximum data path frequency for the
synchronous configuration.
When calculating external asynchronous frequencies, use
t
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
which of 1/(t
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
The parameter t
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If t
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
AS1
if all inputs are on the dedicated input pins.
EXP
TM
EXP
250
200
150
100
50
FOR
+ t
to t
PIA
0
S1
AWH
S1
) is the lowest frequency. The lowest of these
delay for an input from an I/O pin when
OH
EXP
. Determine which of 1/(t
+ t
V
indicates the system compatibility of this
1
O
to the overall delay. Similarly, there is an
AWL
OUTPUT VOLTAGE (V)
), 1/t
I
OH
OL
2
is greater than the minimum
ACO1
V
Room Temp.
I
CC
3
, or 1/(t
OH
EXP
= 5.0V
to t
CY7C342B
4
WH
EXP
AS1
+ t
+ t
Page 4 of 14
. Determine
WL
5
AS1
), 1/t
SU
) is the
if all
CO1
,