CY7C344 CYPRESS [Cypress Semiconductor], CY7C344 Datasheet - Page 5

• Manufacturer Part Number: CY7C344
• Description: 32-Macrocell MAX EPLD
• Manufacturer: CYPRESS [Cypress Semiconductor]

External Synchronous Switching Characteristics
Document #: 38-03006 Rev. **
Parameter
f
f
f
f
t
Notes:
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output
13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, t
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.
15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states
16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that
17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used
MAX1
MAX2
MAX3
MAX4
OH
8.
9.
This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the
register is synchronously clocked. This parameter is tested periodically by sampling production material.
internal period for an internal state machine configuration. This parameter is tested periodically by sampling production material.
must also control external points, this frequency can still be observed as long as it is less than 1/t
parameter is tested periodically by sampling production material.
no expander logic is used.
clock signal applied to either a dedicated input pin or an I/O pin.
External Maximum Frequency(1/(t
Maximum Frequency with Internal Only
Feedback (1/(t
Data Path Maximum Frequency, least of
1/(t
Maximum Register Toggle Frequency
1/(t
Output Data Stable Time from Synchronous
Clock Input
WL
WL
+ t
+ t
WH
WH
[4, 18]
), 1/(t
)
[4, 17]
CF
S
+ t
+ t
H
S
), or (1/t
))
[4, 15]
Description
CO1
)
[4, 16]
CO1
+ t
S
))
[4, 14]
[7]
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Over Operating Range (continued)
Min.
50.0
50.0
71.4
71.4
83.3
83.3
83.3
83.3
7C344-15
3
3
CO1
. This specification assumes no expander logic is used. This
Max.
Min.
41.6
41.6
62.5
62.5
71.4
71.4
71.4
71.4
7C344-20
3
3
Max.
Min.
33.3
33.3
45.4
45.4
62.5
62.5
62.5
62.5
7C344-25
3
3
S
CY7C344
, is the minimum
Max.
Page 5 of 15
MHz
MHz
MHz
MHz
Unit
ns