MC14555 MOTOROLA [Motorola, Inc], MC14555 Datasheet - Page 5

• Manufacturer Part Number: MC14555
• Description: PCM Codec-Filter
• Manufacturer: MOTOROLA [Motorola, Inc]

complementary outputs. The output of the second amplifier
may be internally connected to the input of the transmit anti–
aliasing filter by bringing the ANLB pin high. The power am-
plifiers can drive unbalanced 300
600
rest of the chip by tying the VPI pin to V BB .
MASTER CLOCKS
ture, only one master clock is used. In normal operation (both
frame syncs clocking), the MCLK X is used as the master
clock, regardless of whether the MCLK R /PDN pin is clocking
or low. The same is true if the part is in transmit half–channel
mode (FS X clocking, FS R held low). But if the codec–filter is
in the receive half–channel mode, with FS R clocking and FS X
held low, MCLK R is used for the internal master clock if it is
clocking; if MCLKR is low, then MCLK X is still used for the
internal master clock. Since only one of the master clocks is
used at any given time, they need not be synchronous.
1.544 MHz, or 2.048 MHz. The frequency that the codec–
filter expects depends upon whether the part is a Mu–Law or
an A–Law part, and on the state of the BCLK R /CLKSEL pin.
The allowable options are shown In Table 1. When a level
(rather than a clock) is provided for BCLK R /CLKSEL, BCLK X
is used as the bit clock for both transmit and receive.
FRAME SYNCS AND DIGITAL I/O
standard timing formats. The Long Frame Sync mode is
used by Motorola’s MC145500 family of codec–filters and the
UDLT family of digital loop transceivers. The Short Frame
Sync mode is compatible with the IDL (Interchip Digital Link)
serial format used in Motorola’s ISDN family and by other
companies in their telecommunication devices. These
codec–filters use the length of the transmit frame sync (FS X )
to determine the timing format for both transmit and receive
unless the part is operating in the receive half–channel
mode.
must be at least three bit clock periods long. The D X and TS X
outputs are enabled by the logical ANDing of FS X and
BCLK X ; when both are high, the sign bit appears at the D X
output. The next seven rising edges of BCLK X clock out the
MOTOROLA
Since the codec–filter design has a single DAC architec-
The master clock frequency must be 1.536 MHz,
These codec–filters can accommodate both of the industry
In the Long Frame Sync mode, the frame sync pulses
Clocked, 1, or Open
BCLK R /CLKSEL
BCLK R /CLKSEL
Table 1. Master Clock Frequency Determination
load; they may be powered down independent of the
0
+ Full Scale
– Full Scale
+ Zero
– Zero
Level
Level
Master Clock Frequency Expected
MC145554/64
1.536 MHz
1.544 MHz
2.048 MHz
Sign Bit
1
1
0
0
Mu–Law (MC145554/64)
loads or a balanced
Chord Bits
MC145557/67
0 0 0
1 1 1
1 1 1
0 0 0
2.048 MHz
1.536 MHz
1.544 MHz
Table 2. PCM Data Format
Step Bits
0 0 0 0
1 1 1 1
1 1 1 1
0 0 0 0
remaining seven bits of the PCM word. The D X and TS X out-
puts return to a high impedance state on the falling edge of
the eighth bit clock or the falling edge of FS X , whichever
comes later. The receive PCM word is clocked into D R on the
eight falling BCLK R edges following an FS R rising edge.
must be one bit clock period long. On the first BCLK X rising
edge after the falling edge of BCLK X has latched FS X high,
the D X and TS X outputs are enabled and the sign bit is pres-
ented on D X . The next seven rising edges of BCLK X clock
out the remaining seven bits of the PCM word; on the eighth
BCLK X falling edge, the D X and TS X outputs return to a high
impedance state. On the second falling BCLK R edge follow-
ing an FS R rising edge, the receive sign bit is clocked into
D R . The next seven BCLK R falling edges clock in the re-
maining seven bits of the receive PCM word.
ceive PCM words.
HALF–CHANNEL MODES
codec–filters can operate in both transmit and receive half–
channel modes. Transmit half–channel mode is entered by
holding FS R low. The VF R O output goes to analog ground
but remains in a low impedance state (to facilitate a hybrid
interface); PCM data at D R is ignored. Holding FS X low while
clocking FS R puts these devices in the receive half–channel
mode. In this state, the transmit input operational amplifier
continues to operate, but the rest of the transmit circuitry is
disabled; the D X and TS X outputs remain in a high imped-
ance state. MCLK R is used as the internal master clock if it is
clocking. If MCLK R is not clocking, then MCLK X is used for
the internal master clock, but in that case it should be syn-
chronous with FS R . If BCLK R is not clocking, BCLK X will be
used for the receive data, just as in the full–channel operat-
ing mode. In receive half–channel mode only, the length of
the FS R pulse is used to determine whether Short Frame
Sync or Long Frame Sync timing is used at D R .
POWER–DOWN
the power–down state. Power–down occurs approximately
2 ms after the last frame sync pulse is received. An alterna-
tive way to put these devices in power–down is to hold the
MCLK R /PDN pin high. When the chip is powered down, the
D X , TS X , and GS X outputs are high impedance, the VF R O,
VPO–, and VPO+ operational amplifiers are biased with a
trickle current so that their respective outputs remain stable
at analog ground. To return the chip to the power–up state,
MCLK R /PDN must be low or clocking and at least one of the
frame sync pulses must be present. The D X and TS X outputs
will remain in a high–impedance state until the second FS X
pulse after power–up.
For Short Frame Sync operation, the frame sync pulses
Table 2 shows the coding format of the transmit and re-
In addition to the normal full–duplex operating mode, these
Holding both FS X and FS R low causes the part to go into
MC145554 MC145557 MC145564 MC145567
Sign Bit
1
1
0
0
A–Law (MC145557/67)
Chord Bits
0 1 0
1 0 1
1 0 1
0 1 0
Step Bits
1 0 1 0
0 1 0 1
0 1 0 1
1 0 1 0
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