MC146805E2CFN INNOVASIC [InnovASIC, Inc], MC146805E2CFN Datasheet - Page 15

• Manufacturer Part Number: MC146805E2CFN
• Description: Microprocessor Unit
• Manufacturer: INNOVASIC [InnovASIC, Inc]

IA6805E2
Microprocessor Unit
Timer:
Copyright
innovASIC
(PIN 37)
The MPU contains a single 8-bit software programmable counter driven by a 7-bit software
programmable prescaler. The counter may be loaded under program control and decrements
to zero. When the counter decrements to zero, the timer interrupt request bit in the timer
control register (TCR7) is set. Figure 13 shows a block diagram of the timer. If the timer
mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, an
interrupt request is generated. After completion of the current instruction, the current state
of the machine is pushed onto the stack. The timer interrupt vector address is then fetched
from locations $1FF8 and $1FF9 and the interrupt routine is executed, unless the MPU was
in the WAIT mode in which case the interrupt vector address in locations $1FF6 and $1FF7
is fetched. Power-On-Reset causes the counter to set to $FF.
TIMER
INTERNAL
CLOCK
2002
The End of Obsolescence
NOTE: 1. Prescaler and counter are clocked on the falling edge of the internal
TIMER_n
2. Counter is written to during Data Strobe (DS) and counts down continuously.
TCR4 TCR5
DISABLE_n
ENABLE /
clock (AS) or external input.
Figure 13. Timer Block Diagram
INTERNAL_n / EXTERNAL
ENG21108140100
CLK
CLK
Page 15 of 31
EXT
INT
2 - TO - 1
MUX
SOFTWARE FUNCTIONS
PRESCALER
TCR3 TCR2 TCR1 TCR0
(7 BITS)
SETTING TCR3 CLEARS
As of Production Version 00
PRESCALER TO ÷ 1
READ
COUNTER
(8 BITS)
WRITE
Data Sheet
www.innovasic.com
Customer Support:
1-888-824-4184
INTERRUPT
INTERRUPT
CONTROL