CY7C64013 CYPRESS [Cypress Semiconductor], CY7C64013 Datasheet - Page 22

• Manufacturer Part Number: CY7C64013
• Description: Full-Speed USB (12 Mbps) Function
• Manufacturer: CYPRESS [Cypress Semiconductor]

12.0
Internal hardware supports communication with external devices through two interfaces: a two-wire I
a HAPI for 1, 2, or 3 byte transfers. The I
14.0, share a common configuration register (see Figure 12-1). All bits of this register are cleared on reset.
Bits [7,1:0] of the HAPI/I
Bits [5:2] are used in HAPI mode only, and are described in Section 14.0. Table 12-1 shows the HAPI port configurations, and
Table 12-2 shows I
packages, and to allow simultaneous HAPI and I
HAPI operation is enabled whenever either HAPI Port Width Bit (Bit 1 or 0) is non-zero. This affects GPIO operation as described
in Section 14.0. I
Table 12-1. HAPI Port Configuration
Table 12-2. I
Document #: 38-08001 Rev. **
I
2
C Position
R/W
7
I
I
Port Width
2
2
C Position
Bits[1:0]
C and HAPI Configuration Register
Bit[7]
2
C Port Configuration
11
L3
10
01
00
11
X
0
1
2
D3
C compatible blocks must be separately enabled as described in Section 13.0.
Reserved
2
C pin location configuration options. These I
10
L2
6
D2
2
C Configuration Register control the pin out configuration of the HAPI and I
9
L1
D1
Figure 12-1. HAPI/I
8
L0
24 Bits: P3[7:0], P1[7:0], P0[7:0]
LEMPTY
D0
Polarity
R/W
16 Bits: P1[7:0], P0[7:0]
5
7
No HAPI Interface
2
HAPI Port Width
Port Width
D7
C compatible interface and HAPI functions, discussed in detail in Sections 13.0 and
8 Bits: P0[7:0]
Bit[1]
Figure 11-3. Timer Block Diagram
6
1
0
0
D6
2
C compatible operation.
2
C Configuration Register 0x09 (read/write)
Polarity
5
DRDY
R/W
D5
4
4
D4
3
Latch Empty
2
I
I
I
2
2
2
C compatible options exist due to pin limitations in certain
D3
C on P2[1:0], 0:SCL, 1:SDA
C on P1[1:0], 0:SCL, 1:SDA
C on P2[1:0], 0:SCL, 1:SDA
R
3
2
D2
I
2
C Position
1
D1
Data Ready
8
0
D0
R
2
1.024-ms Interrupt
128- s Interrupt
1-MHz Clock
To Timer Register
Width Bit 1
HAPI Port
2
C compatible interface, and
R/W
2
C compatible interfaces.
1
CY7C64013
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Width Bit 0
HAPI Port
R/W
0