CY7C64013 CYPRESS [Cypress Semiconductor], CY7C64013 Datasheet - Page 28

• Manufacturer Part Number: CY7C64013
• Description: Full-Speed USB (12 Mbps) Function
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 16-1. Interrupt Vector Assignments
A pending address can be read from the Interrupt Vector Register (Figure 16-4). The value read from this register is only valid if
the Global Interrupt bit has been disabled, by executing the DI instruction or in an Interrupt Service Routine before interrupts have
been re-enabled. The value read from this register is the interrupt vector address; for example, a 0x06 indicates the 1 ms timer
interrupt is the highest priority pending interrupt.
16.2
Interrupt latency can be calculated from the following equation:
Interrupt latency =
For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is
issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock periods is 20 / 12 MHz = 1.667 s.
16.3
The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists on the upstream USB port for
12–16 s (the Reset may be recognized for an SE0 as short as 12 s, but is always recognized for an SE0 longer than 16 s).
SE0 is defined as the condition in which both the D+ line and the D– line are LOW. Bit 5 of the Status and Control Register is set
to record this event. The interrupt is asserted at the end of the Bus Reset. If the USB reset occurs during the start-up delay
following a POR, the delay is aborted as described in Section 7.1. The USB Bus Reset Interrupt is generated when the SE0 state
is deasserted.
A USB Bus Reset clears the following registers:
Document #: 38-08001 Rev. **
Reserved
SIE Section:USB Device Address Registers (0x10, 0x40)
7
Interrupt Vector Number
Interrupt Latency
USB Bus Reset Interrupt
Not Applicable
Reserved
10
12
11
1
2
3
4
5
6
7
8
9
(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +
(5 clock cycles for the JMP instruction)
6
Figure 16-4. Interrupt Vector Register 0x23 (read only)
Reserved
5
Vector Bit 4
Interrupt
ROM Address
R
4
0x000A
0x000C
0x000E
0x0000
0x0002
0x0004
0x0006
0x0008
0x0010
0x0012
0x0014
0x0016
0x0018
Vector Bit 3
Interrupt
R
3
Execution after Reset begins here
USB Bus Reset interrupt
128- s timer interrupt
1.024-ms timer interrupt
USB Address A Endpoint 0 interrupt
USB Address A Endpoint 1 interrupt
USB Address A Endpoint 2 interrupt
USB Address A Endpoint 3 interrupt
USB Address A Endpoint 4 interrupt
Reserved
DAC interrupt
GPIO / HAPI interrupt
I
2
C interrupt
Vector Bit 2
Interrupt
R
2
Vector Bit 1
Function
Interrupt
R
1
CY7C64013
CY7C64113
Page 28 of 48
Reads ‘0’
R
0