CY7C68300C CYPRESS [Cypress Semiconductor], CY7C68300C Datasheet - Page 11

• Manufacturer Part Number: CY7C68300C
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document 001-05809 Rev. *A
Table 1. AT2LP Pin Descriptions
Additional Pin Descriptions
The following sections provide additional pin information.
DPLUS, DMINUS
DPLUS and DMINUS are the USB signaling pins; they must
be tied to the D+ and D– pins of the USB connector. Because
they operate at high frequencies, the USB signals require
special consideration when designing the layout of the PCB.
See
Storage Designs” on page 39
tions.
When RESET# is released, the assertion of the internal pull
up on D+ is gated by a combination of the state of the
VBUS_ATA_ENABLE pin, the value of configuration address
0x08 bit 0 (DRVPWRVLD Enable), and the detection of a
non-removable ATA/ATAPI drive on the IDE bus. See
for a description of this relationship.
Table 2. D+ Pull Up Assertion Dependencies
SCL, SDA
The clock and data pins for the I
the configuration EEPROM and to 2.2K pull up resistors tied
to V
TQFP
100
ATA/ATAPI Drive Detected
100
DRVPWRVLD Enable Bit
CC
“General PCB Layout Recommendations For USB Mass
[3]
. If no EEPROM is used in the design, the SCL and SDA
State of D+ pull up
QFN
54
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode)
56
VBUS_ATA_EN
[3]
SSOP
56
5
Yes
for PCB layout recommenda-
1
1
1
Pin Name
ATAPUEN
2
C port must be connected to
(NC)
No
1
1
1
Yes
1
0
1
No
1
0
0
Type
Pin
IO
Yes
0
1
0
Table 2
No
Default State
0
1
0
at Startup
pins must still be connected to pull up resistors. The SCL and
SDA pins are active for several milliseconds at startup.
XTALIN, XTALOUT
The AT2LP requires a 24 MHz (
internal timing. Typically, a 24 MHz (12 pF, 500 μW,
parallel-resonant, fundamental mode) crystal is used, but a 24
MHz square wave (3.3V, 50/50 duty cycle) from another
source can also be used. If a crystal is used, connect its pins
to XTALIN and XTALOUT, and also through 12 pF capacitors
to GND as shown in
used, apply it to XTALIN and leave XTALOUT unconnected.
12pF
Bus-powered ATA pull up voltage source (see
“ATAPUEN” on page
Alternate function: General purpose input when the
EEPROM configuration byte 8 has bit 7 set to ‘1’. The
input value is reported through EP1IN (byte 0, bit 2).
Figure 7. XTALIN/XTALOUT Diagram
XTALIN
CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Figure
24MHz Xtal
Pin Description
14).
7. If an alternate clock source is
(continued)
±
100 ppm) signal to derive
XTALOUT
Page 11 of 42
12pF
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