M41T60_05 STMICROELECTRONICS [STMicroelectronics], M41T60_05 Datasheet - Page 5

• Manufacturer Part Number: M41T60_05
• Description: Serial access real-time clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M41T60
2
2.1
2.1.1
2.1.2
2.1.3
Operation
The M41T60 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1.
2.
3.
4.
5.
6.
7.
8.
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
●
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain High.
Start data transfer
A change in the state of the data line, from High to Low, while the clock is High, defines the
START condition.
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the
STOP condition.
Seconds Register
Minutes Register
Hours Register
Day Register
Date Register
Century/Month Register
Years Register
Calibration Register
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is High.
Changes in the data line while the clock line is High will be interpreted as control
signals.
Operation
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