CDP68HC68A2M96 INTERSIL [Intersil Corporation], CDP68HC68A2M96 Datasheet - Page 12

• Manufacturer Part Number: CDP68HC68A2M96
• Description: CMOS Serial 10-Bit A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

The contents of Data Registers are not guaranteed following
an abort. Writing a $00 to the MSR is equivalent to a reset.
To synchronously stop conversions in Modes 2 or 3 set the
SAR to $00 (See Mode 2 and Mode 3).
Analog Inputs
Shown in Figure 5 is a simplified equivalent circuit
representing the input to the Analog to Digital Converter
through the multiplexer as seen from each AIn pin.
Due to the nature of the switched capacitor array used by the
successive approximation A/D, two important points are
noted here:
A property of capacitive input is the intrinsic sample and
hold function. This provides all that is necessary to
accurately sample a point on an input waveform within the
input bandwidth shown in the specifications (under 1.5
conversion oscillator cycles).
The input to the capacitor network appears as an RC
network with a time constant and therefore places
constraints on the source impedance. The charging time and
therefore the accuracy of the conversion will be adversely
affected by increasing the source impedance.
It is recommended to set the conversion oscillator frequency
in accordance with the input impedance in order to allow
sufficient time (the 1.5 T
waveform through the modeled input low pass filter network
which includes the input source in a series circuit with the
internal impedance.
1. A write to the MSR
2. A write to the CSR
3. A write to the SAR with ENC and/or SAE = 1
4. A read of any Data Register
FIGURE 5A. ANALOG INPUT DURING SAMPLE TIME
SIGNAL
INPUT
D1
D2
OSC
V
CC
12
cycles) to sample a changing
85Ω
R1
400pF
C1
V
V1
2.5V
CDP68HC68A2
The time constant (τ) for the input network is R
8τ is required during the first 1.5 sample clock cycles to
sufficiently encode 10-bit conversion. Therefore, 1.5 T
and T
For example, if R
432kHz, and T
of 32µs. An internal C
The maximum frequency is limited by the device
specification (see characteristics) and by the (R
input resistance:
For example, for a 1MHz sample clock R
R
τ
T
f
R
then f
SAMPLE
FIGURE 5B. ANALOG INPUT DURING HOLD AND IDLE TIME
EFF
S
=
S
R
≤
=
EFF
[
S
SAMPLE
SIGNAL
1/f
(
=
4.688
INPUT
≥ 5.33 R
R
SAMPLE
C
S
≤
NET
+
(
×
4.688
R
≤
10
S
NET
=
[
5.33 R
EFF
= 2.3µs. This yields a 10-bit conversion time
8
,
(
S
R
""
×
,
S
)/f
= 1000, f
C
10
C.
(
+
NET
SAMPLE
OSC
8
50Ω
S
)
+
⁄
D1
D2
(
=
85Ω
R
) 400pF.
≥ 68pF, see chart.
400pF and R
S
V
SAMPLE
CC
,
+
] 85Ω.
) 400pF
85Ω
–
,
)
.
must be less than
]
–
NET
S
1,
max = 385Ω.
=
50Ω.
EFF
OPEN
CIRCUIT
S
) Series
C
NET
S
≥ 8τ
.