CDP68HC68A2M96 INTERSIL [Intersil Corporation], CDP68HC68A2M96 Datasheet - Page 6

• Manufacturer Part Number: CDP68HC68A2M96
• Description: CMOS Serial 10-Bit A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

Serial Communications
Hardware Interface
All communications between the A2 and the controlling
processor are carried out over the Serial Peripheral Interface
(SPI) bus lines (MOSI, MISO, SCK, and CE). The SPI bus is
directly compatible with the SPI facilities of CDP68HC05
microcontrollers. Data is transmitted over the MISO and
MOSI lines synchronous with SCK. Transfers are done most
significant bit first.
The A2 acts as a “slave” device. The controlling “master”
signals the A2 that a SPI transfer is to take place by raising
CE and clocking SCK. A single shift register is used for
transferring data in and out of the A2. Whenever CE and
SCK are activated, data is shifted from the master to the A2
over the Master-Out-Slave-In (MOSI) line and,
simultaneously, during read operations, data is shifted to the
master from the A2 over the Master-In-Slave-Out (MISO)
line. Note that SCK must be provided by the master for both
reads and writes.
(READ
ONLY)
SCK a
SCK
MOSI
MISO
CE
b
T
dsu
T
dh
T
P
$0E
$00
$01
$0F
$10
$11
$12
$13
D7
FIGURE 2. TIMING DIAGRAM FOR SERIAL PERIPHERAL INTERFACE
CONTROL/STATUS REGISTERS
6
CHANNEL SELECT REGISTER
START ADDRESS REGISTER
MODE SELECT REGISTER
HIGH DATA REGISTER 0
HIGH DATA REGISTER 7
LOW DATA REGISTER 0
LOW DATA REGISTER 7
FIGURE 1. A PROGRAMMER’S MODEL OF THE CDP68HC68A2
STATUS REGISTER
DATA REGISTERS
D6
T
dod
D5
CDP68HC68A2
D4
To accommodate various hardware systems, the A2 can
shift data on either the rising or falling edge of SCK. The
“active” edge is automatically determined by the A2. At the
moment that CE is first brought to a high level, the state of
SCK is latched. This latched state determines the
interpretation of SCK. If SCK is low when CE is activated,
data is shifted out on MISO on each rising edge of SCK and
data is latched from MOSI on each falling edge of SCK (see
SCK
is shifted out on MISO on each falling edge of SCK and data
is latched from MOSI on each rising edge of SCK (see SCK
in Figure 2).
Hardware Interfacing to CDP68HC05 Controllers
When interfacing the A2 to CDP68HC05 controllers, set
CPHA = 1 and CPOL = (0 or 1) in the SPI control register. Note
that SCK pulses are generated only when data is written to the
SPI Data Register in a CDP68HC05. Reading data from or
writing data to the A2 requires writing data to the SPI Data
Register. The data will be ignored by the A2 for read operations.
The read data is available to the CDP68HC05 in the SPI Data
Register when SPIF is true in the SPI Status Register.
D3
CHANNEL ADDRESS REGISTER
a
in Figure 2). If SCK is high when CE is activated, data
OUT
D2
TO
A
D
IN
TO
M
U
D1
X
8
1
AI0
AI1
AI2
AI3
AI4
AI5
AI6
AI7
D0
b