ISL5217_05 INTERSIL [Intersil Corporation], ISL5217_05 Datasheet - Page 15

• Manufacturer Part Number: ISL5217_05
• Description: Quad Programmable Up Converter
• Manufacturer: INTERSIL [Intersil Corporation]

The resulting complex output is given by the following
equations.
Re mixer (20:0) = I(20:0) * cos(18:0) - Q(20:0) * sin(18:0)
Im mixer (20:0) = Q(20:0) * cos(18:0) + I(20:0) * sin(18:0)
(Vector weighting for block diagram)
I (20:0) = 2
Q (20:0) = 2
sin (18:0) = 2
cos (18:0) = 2
Re mixer(20:0) = 2
Im mixer(20:0) = 2
Output Processing
Output processing sums the modulated output of each
channel to provide multi-carrier outputs. There are four
4-channel summers, which combined with the outputs IOUT,
QOUT, and bidirectional outputs IIN and QIN can be
configured by the user to support eight output modes. The
output mode is determined by Device Control 0x78 bits 9:8
and Main Control 0xc, bit 7.
Output Modes
Cascade Mode: In this mode IIN<19:0> and QIN<19:0> are
configured as inputs for the real and imaginary cascade
inputs. This is the only mode where IIN and QIN are
configured as inputs.
The cascade input allows for more than four multi-channel
transmissions by summing the complex modulated signals
from other device’s with the four channel summer. A cascade
chain of four devices allows up to sixteen carriers. Each
device delays it’s 4-channel summation to align with the
cascade in from the previous device. Device Control 0x78
bits 2:1, Cascade delay <1:0>, identifies the position in the
NOTE: re CASout is re SUM1 + re CASinput, im CASout is im SUM1 + im CAS in.
Cascade Mode
Real
Imaginary
Muxed I/Q
Muxed I/Q at 2X Rate
Complex Output Mode 1 1 (Ch. 0 only)
Complex Output Mode 2 1 (Ch. 2 only)
Complex Output Mode 3 1 (Ch. 0 and 2)
OUTPUT MODE
1
1
.. 2
... 2
0
0
... 2
... 2
-19
-19
-18
1
-18
1
... 2
... 2
-19
-19
0X0C, BIT 7
CONTROL
COMPLEX
OUTPUT
MODE
MAIN
0
0
0
0
0
0
0
15
0X78, BITS 9:8
CONTROL
OUTPUT
MODE
MAIN
00
01
10
11
11
01
01
01
01
01
TABLE 7. OUTPUT MODES
0X78, BIT 10
OUTPUT 2X
CONTROL
SELECT
MAIN
0
0
0
0
0
1
1
0
0
0
ISL5217
ISTRB CLK IIN<19:0> QIN<19:0>
X
X
X
X
1
0
X
X
X
X
cascade chain to select the appropriate delay. Device
Control 0x78, bit 3, Cascade input enable, zeroes the
cascade-in data when the port is not in use. The output of
the summation is saturated to prevent roll-over.
Real: Real data is output on IIN, QIN, IOUT, and QOUT.
Imag: Imaginary data is output on IIN, QIN, IOUT, and
QOUT.
Muxed I/Q: The output data alternates between real and
imaginary on clock time boundaries. The output signal
ISTRB is asserted when the output data is real. The ISTRB
is enabled by Device Control 0x78, bit 5. In this mode, the
I/Q samples are decimated by two. This is the only mode in
which the output data is decimated.
NOTE: When in Muxed I/Q mode the output order is I then
Q.
Muxed I/Q at 2x rate: The output data alternates between
real and imaginary within a clock time boundary. The output
data is real when the clock is high, and imaginary when the
clock is low. All I/Q samples are output, and there is no
decimation of the output stream. Care should be utilized to
ensure sufficient set-up time is achieved for the downstream
device in the application, as data is alternating I then Q
between clock boundaries.
Complex out 1: In this mode, complex data is output on IIN
and QIN, while real data is output on IOUT and QOUT.
Complex out 2: In this mode, real data is output on IIN and
QIN, while complex data is output on IOUT and QOUT.
Complex out 3: In this mode, complex data is output on IIN
and QIN and complex data is output on IOUT and QOUT.
X
X
X
X
X
X
X
X
1
0
im SUM1
im SUM1
im SUM1
re SUM1
re SUM1
re SUM1
re SUM1
re SUM1
re SUM1
Input re
im SUM2
im SUM2
im SUM2
im SUM1
im SUM1
re SUM2
re SUM2
re SUM2
re SUM2
Input im
IOUT<19:0>
re CASout
im SUM3
im SUM3
im SUM3
re SUM3
re SUM3
re SUM3
re SUM3
re SUM3
re SUM3
QOUT<19:0>
im CASout
im SUM4
im SUM4
im SUM4
im SUM3
im SUM3
re SUM4
re SUM4
re SUM4
re SUM4
July 8, 2005
FN6004.3