ISL5217_05 INTERSIL [Intersil Corporation], ISL5217_05 Datasheet - Page 16

• Manufacturer Part Number: ISL5217_05
• Description: Quad Programmable Up Converter
• Manufacturer: INTERSIL [Intersil Corporation]

4-Channel Summers
Cascade Input
When in the complex cascade mode the 4-channel summer
re 1 and im 1 are summed with the real and imaginary
cascade inputs. The cascade input allows for more than four
multi-channel transmissions by summing the complex
modulated signals from other device’s. A cascade chain of
four devices allows up to sixteen carriers. Figure 15
illustrates cascading multiple devices. Each device delays it’s
4-channel summation to align with the cascade in from the
previous device. Device Control 0x78, bits 2:1 identifies the
position in the cascade chain. Device Control 0x78, bit 3
zeroes the cascade-in data when the port is not in use. The
output of the summation is saturated to prevent roll-over.
MAIN CONTROL 0X78, BITS
9:8 OUTPUT MODE
01,10,11
01,10,11
01,10,11
01,10,11
00
00
00
00
FIGURE 15. CASCADED QPUCs
µP
µP
µP
µP
SCLKX
FSRX
SDX
SCLKX
FSRX
SDX
SCLKX
FSRX
SDX
SCLKX
FSRX
SDX
MASTER
ISL5217
ISL5217
ISL5217
ISL5217
QPUC
SLAVE
QPUC
SLAVE
QPUC
SLAVE
QPUC
16
OUTEN
<1:0>
00
01
10
11
00
01
10
11
I OUT <19:0>
Q OUT <19:0>
SYNCO
UPDX
Q IN <19:0>
I OUT <19:0>
Q OUT <19:0>
UPDX
Q IN <19:0>
I OUT <19:0>
Q OUT <19:0>
UPDX
Q IN <19:0>
I OUT <19:0>
Q OUT <19:0>
I IN <19:0>
I IN <19:0>
I IN <19:0>
TABLE 8. INPUT/OUTPUT MODES
<19:0>
Output
Output
Input
Input
Input
Input
Input
Input
IIN
ISL5217
†
Output Formatter
offset binary. The OFFBIN pin is used to select the output
format. The output ranges from 0x8001 to 0x7FFF for two’s
complement and from 0x0001 - 0xFFFF for offset binary.
Microprocessor Interface
NOTE: See Appendix A, Errata Sheet
The microprocessor interface allows the QPUC to appear as
a memory mapped peripheral to the µP. Configuration data,
I/Q sample data and RAM data can be accessed through
this interface. The interface consists of a 16 bit bidirectional
data bus, P<15:0>, seven bit address bus, A<6:0>, a write
strobe (WR), a read strobe (RD) and a chip enable (CE).
Two µP interface modes are supported through the input pin
RDMODE
read and write strobe inputs. When high the device is
configured for a common Read/Write and data strobe inputs
This mode redefines RD into Read/Write Strobe and WR
into Data Strobe.
The address space is partitioned into five directly accessible
regions, one for top control and one for each of the four
channels. The Device Control space allows for configuration
parameters that effect the entire device, cascade, output
modes, and routing. The channel space allows for
configuration parameters and sample data.
The master registers for the configuration data and I/Q
sample data are located in these areas. There is a master
The output can be formatted in either twos complement or
MOD(20:0)
I IN<19:0>
ALL REGISTERS ARE CLOCKED AT CLK
CASZ
<19:0>
Output
Output
FIGURE 16. CASCADE INPUT BLOCK DIAGRAM
Input
Input
Input
Input
Input
Input
QIN
.
When low the device is configured for separate
20
21
>
>
G
G
<19:0>
R
E
R
E
Output
Output
Output
Output
IOUT
HI-Z
HI-Z
HI-Z
HI-Z
∑
22
CIRCUITRY
SATURATE
<19:0>
Output
Output
Output
Output
QOUT
20
HI-Z
HI-Z
HI-Z
HI-Z
I OUT<19:0>
July 8, 2005
FN6004.3
.