MAX533ACEE MAXIM [Maxim Integrated Products], MAX533ACEE Datasheet - Page 10

• Manufacturer Part Number: MAX533ACEE
• Description: 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
• Manufacturer: MAXIM [Maxim Integrated Products]

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
All four DAC registers are updated with shift-register
data. This command allows all DACs to be set to any
analog value within the reference range. This command
can be used to substitute CLR if code 00 hex is pro-
grammed, which clears all DACs.
Shuts down all output buffer amplifiers, reducing sup-
ply current to 10µA max.
(LDAC = X)
(LDAC = X, PDE = H)
10
A1
A1
1
1
A1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
______________________________________________________________________________________
A0
A0
0
1
C1
C1
0
0
A0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
Load All DACs with Shift-Register Data
C0
C0
0
0
12-BIT SERIAL WORD
D7
D7
x
C1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
1
D6
D6
x
D5
D5
x
C0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
8-Bit Data
D4
D4
Software Shutdown
x
D7 . . . . . . . . D0
D3
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
D3
8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data
x
D2
D2
x
D1 D0
D1 D0
x
x
LDAC
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
User-programmable logic output for controlling another
device across an isolated interface. Example devices
are gain control of an amplifier, a 4mA to 20mA amplifi-
er, and a polarity output for a motor speed control.
The NOP command (no operation) allows data to be
shifted through the MAX533 shift register without affect-
ing the input or DAC registers. This is useful in daisy
chaining (also see the Daisy Chaining Devices section).
(LDAC = X)
(LDAC = X)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
A1
0
0
1
Load input register A; all DAC outputs unchanged.
Load input register B; all DAC outputs unchanged.
Load input register C; all DAC outputs unchanged.
Load input register D; all DAC outputs unchanged.
Load input register A; all DAC outputs updated
Load input register B; all DAC outputs updated
Load input register C; all DAC outputs updated
Load input register D; all DAC outputs updated.
Software LDAC commands. Update all DACs from
their respective input registers. Also bring the part out
of shutdown mode.
Load all DACs with shift-register data. Also bring the
part out of shutdown mode.
Software shutdown (provided PDE is high)
UPO goes low.
UPO goes high.
No operation (NOP); shift data in shift registers.
Set DOUT phase—SCLK rising (mode 1). DOUT
clocked out on rising edge of SCLK. All DACs updated
from their respective input registers.
Set DOUT phase—SCLK falling (mode 0). DOUT
clocked out on falling edge of SCLK. All DACs up-
dated from their respective registers (default).
A0
0
1
1
C1
0
0
0
C0
0
x
x
User-Programmable Output (UPO)
D7
x
x
x
FUNCTION
D6
x
x
x
x
x
D5
x
x
x
D4
No Operation (NOP)
x
x
x
D3
x
x
x
D2
x
x
x
D1
Output
x
UPO
High
Low
D0
x