MAX533ACEE MAXIM [Maxim Integrated Products], MAX533ACEE Datasheet - Page 11

• Manufacturer Part Number: MAX533ACEE
• Description: 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
• Manufacturer: MAXIM [Maxim Integrated Products]

For this command, the data bits are “Don't Cares.” As
an example, three MAX533s are daisy chained (A, B,
and C), and devices A and C need to be updated. The
36-bit-wide command would consist of one 12-bit word
for device C, followed by an NOP instruction for device
B and a third 12-bit word with data for device A. At CS’s
rising edge, device B will not change state.
Mode 1 resets the serial-output DOUT to transition at
SCLK’s rising edge. Once this command is issued,
DOUT’s phase is latched and will not change except on
power-up or if the specific command to set the phase
to falling edge is issued.
This command also loads all DAC registers with the con-
tents of their respective input registers, and is identical to
the “LDAC” command.
This command resets DOUT to transition at SCLK’s falling
edge. The same command also updates all DAC registers
with the contents of their respective input registers, identical
to the “LDAC” command.
LDAC is typically used in 4-wire interfaces (Figure 7). This
command is level sensitive, and it allows asynchronous
hardware control of the DAC outputs. With LDAC low, the
DAC registers are transparent, and any time an input regis-
ter is updated, the DAC output immediately follows.
Strobing the CLR pin low causes an asynchronous
clear of input and DAC registers and sets all DAC out-
puts to zero. Similar to the LDAC pin, CLR can be
invoked at any time, typically when the device is not
selected (CS = H). When the DAC data is all zeros, this
function is equivalent to the “Update all DACs from Shift
Registers” command.
(LDAC = x)
(LDAC = x)
A1
A1
1
1
Set DOUT Phase—SCLK Falling (Mode 0, Default)
A0
A0
1
0
C1
C1
1
1
Set DOUT Phase—SCLK Rising (Mode 1)
C0
C0
0
0
______________________________________________________________________________________
D7
D7
x
x
D6
D6
x
x
LDAC Operation (Hardware)
D5
D5
x
x
Clear DACs with
D4
D4
x
x
2.7V, Low-Power, 8-Bit Quad DAC
D3
D3
x
x
with Rail-to-Rail Output Buffers
D2
D2
x
x
D1
D1 D0
x
x
CLR
D0
x
x
DOUT is the internal shift register’s output. DOUT can
be programmed to clock out data on SCLK’s falling
edge (mode 0) or rising edge (mode 1). In mode 0, out-
put data lags input data by 12.5 clock cycles, maintain-
ing compatibility with Microwire and SPI. In mode 1,
output data lags input data by 12 clock cycles. On
power-up, DOUT defaults to mode 0 timing. DOUT
never three-states; it always actively drives either high
or low and remains unchanged when CS is high.
Figure 4. Connections for Microwire
Figure 5. Connections for SPI/QSPI
MAX533
MAX533
SCLK
SCLK
DIN
DIN
CS
CS
CPOL = 0, CPHA = 0
SK
SO
I/0
MOSI
SCK
I/0
Serial Data Output
MICROWIRE
SPI/QSPI
PORT
PORT
11