MAX533ACEE MAXIM [Maxim Integrated Products], MAX533ACEE Datasheet - Page 9

• Manufacturer Part Number: MAX533ACEE
• Description: 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
• Manufacturer: MAXIM [Maxim Integrated Products]

At power-on, the serial interface and all digital-to-
analog converters (DACs) are cleared and set to code
zero. The serial data output (DOUT) is set to transition
on SCLK's falling edge.
The MAX533 communicates with microprocessors
through a synchronous, full-duplex, 3-wire interface
(Figure 1). Data is sent MSB first and can be transmit-
ted in one 4-bit and one 8-bit (byte) packet or in one
12-bit word. If a 16-bit word is used, the first four bits
are ignored. A 4-wire interface adds a line for LDAC
and allows asynchronous updating. The serial clock
(SCLK) synchronizes the data transfer. Data is transmit-
ted and received simultaneously.
Figure 2 shows the detailed serial-interface timing.
Please note that the clock should be low if it is stopped
between updates. DOUT does not go into a high-
impedance state if the clock idles or CS is high.
Serial data is clocked into the data registers in MSB-first
format, with the address and configuration information
preceding the actual DAC data. Data is clocked in on
SCLK’s rising edge while CS is low. Data at DOUT is
clocked out 12 clock cycles later, either at SCLK’s falling
edge (default or mode 0) or rising edge (mode 1).
Chip select (CS) must be low to enable the DAC. If CS
is high, the interface is disabled and DOUT remains
unchanged. CS must go low at least 40ns before the
first rising edge of the clock pulse to properly clock in
the first bit. With CS low, data is clocked into the
MAX533’s internal shift register on the rising edge of
the external serial clock. Always clock in the full 12 bits
because each time CS goes high the bits currently in
the input shift register are interpreted as a command.
SCLK can be driven at rates up to 10MHz.
Figure 3. Serial Input Format
_______________Detailed Description
DOUT
A1 A0 C1 C0 D7 D6
THIS IS THE FIRST BIT SHIFTED IN
CONTROL AND
ADDRESS BITS
_______________________________________________________________________________________
MSB
8-BIT DAC DATA
...
Serial Interface
2.7V, Low-Power, 8-Bit Quad DAC
D1
with Rail-to-Rail Output Buffers
D0
LSB
DIN
The 12-bit serial input format shown in Figure 3 com-
prises two DAC address bits (A1, A0), two control bits
(C1, C0), and eight bits of data (D7...D0).
The 4-bit address/control code configures the DAC as
shown in Table 1.
When performing a single update operation, A1 and A0
select the respective input register. At the rising edge
of CS, the selected input register is loaded with the cur-
rent shift-register data. All DAC outputs remain
unchanged. This preloads individual data in the input
register without changing the DAC outputs.
This command directly loads the selected DAC register at
CS’s rising edge. A1 and A0 set the DAC address. Current
shift-register data is placed in the selected input and DAC
registers.
For example, to load all four DAC registers simultaneously
with individual settings (DAC A = 0.5V, DAC B = 1V,
DAC C = 1.5V, and DAC D = 2V), four commands are
required. First, perform three single input register
update operations for DACs A, B, and C (C1 = 0). The
final command loads input register D and updates all
four DAC registers from their respective input registers.
All DAC registers are updated with the contents of their
respective input registers at CS’s rising edge. With the
exception of using CS to execute, this performs the
same function as the asynchronous LDAC.
(LDAC = H)
(LDAC = H)
(LDAC = 1)
A1
Address
Address
A1
A1
0
Load Input Register, DAC Registers Unchanged
A0
A0
A0
1
Serial Input Data Format and Control Codes
C1
C1
C1
0
0
1
C0
C0
C0
0
1
1
D7
D7
D7
x
Load Input and DAC Registers
D6
D6
D6
Software “
x
(Single Update Operation)
D5
D5
D5
x
8-Bit Data
8-Bit Data
D4
D4
D4
x
LDAC
D3
D3
D3
x
” Command
D2
D2
D2
x
D1
D1
D1
x
D0
D0
D0
x
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