AD9211_07 AD [Analog Devices], AD9211_07 Datasheet

AD9211_07

Manufacturer Part Number

AD9211_07

Description

10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter

Manufacturer

AD [Analog Devices]

Datasheet

1.AD9211_07.pdf (28 pages)

Current page: 1 of 28
Download datasheet (2Mb)

FEATURES

SNR = 60.1 dBFS @ f

ENOB of 9.7 @ f

SFDR = −80 dBc @ f

Excellent linearity

LVDS at 300 MSPS (ANSI-644 levels)

700 MHz full power analog bandwidth

On-chip reference, no external decoupling required

Integrated input buffer and track-and-hold

Low power dissipation

Programmable input voltage range

1.8 V analog and digital supply operation

Selectable output data format (offset binary, twos

Clock duty cycle stabilizer

Integrated data capture clock

APPLICATIONS

Wireless and wired broadband communications

Cable reverse path

Communications test equipment

Radar and satellite subsystems

Power amplifier linearization

GENERAL DESCRIPTION

The AD9211 is a 10-bit monolithic sampling analog-to-digital

converter optimized for high performance, low power, and ease

of use. The product operates at up to a 300 MSPS conversion

rate and is optimized for outstanding dynamic performance

in wideband carrier and broadband systems. All necessary

functions, including a track-and-hold (T/H) and voltage

reference, are included on the chip to provide a complete

signal conversion solution.

The ADC requires a 1.8 V analog voltage supply and a

differential clock for full performance operation. The digital

outputs are LVDS (ANSI-644) compatible and support either

twos complement, offset binary format, or Gray code. A data

clock output is available for proper output data timing.

Fabricated on an advanced CMOS process, the AD9211 is

available in a 56-lead LFCSP, specified over the industrial

temperature range (−40°C to +85°C).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

DNL = ±0.1 LSB typical

INL = ±0.2 LSB typical

437 mW @ 300 MSPS—LVDS SDR mode

410 mW @ 300 MSPS—LVDS DDR mode

1.0 V to 1.5 V, 1.25 V nominal

complement, Gray code)

up to 70 MHz @ 300 MSPS (−1.0 dBFS)

up to 70 MHz @ 300 MSPS

10-Bit, 200 MSPS/250 MSPS/300 MSPS,

1.8 V Analog-to-Digital Converter

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

PRODUCT HIGHLIGHTS

CLK+

CLK–

VIN+

VIN–

High Performance—Maintains 60.1 dBFS SNR @

300 MSPS with a 70 MHz input.

Low Power—Consumes only 410 mW @ 300 MSPS.

Ease of Use—LVDS output data and output clock signal

allow interface to current FPGA technology. The on-chip

reference and sample-and-hold provide flexibility in

system design. Use of a single 1.8 V supply simplifies

system power supply design.

Serial Port Control—Standard serial port interface

supports various product functions, such as data

formatting, disabling the clock duty cycle stabilizer, power-

down, gain adjust, and output test pattern generation.

Pin-Compatible Family—12-bit pin-compatible family

offered as AD9230.

TRACK-AND-HOLD

RBIAS

MANAGEMENT

REFERENCE

FUNCTIONAL BLOCK DIAGRAM

CLOCK

PWDN

RESET SCLK SDIO CSB

10-BIT

CORE

SERIAL PORT

ADC

Figure 1.

AGND

STAGING

AVDD (1.8V)

AD9211

OUTPUT

LVDS

AD9211

www.analog.com

DRVDD

DGND

D9 TO D0

OR+

OR–

DCO+

DCO–

Related parts for AD9211_07

Related keywords

AD9211_07 datasheet
AD9211_07 data sheet
AD9211_07 pdf datasheet
AD9211_07 component
AD9211_07 part
AD9211_07 distributor
AD9211_07 RoHS
AD9211_07 datasheet download