AD9211_07 AD [Analog Devices], AD9211_07 Datasheet - Page 24

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AD9211_07

Manufacturer Part Number
AD9211_07
Description
10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter
Manufacturer
AD [Analog Devices]
Datasheet
AD9211
Table 11. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
DS
DH
CLK
S
H
HI
LO
EN_SDIO
DIS_SDIO
Condition (V)
< 0.62
= 0.62
= 0
= 0.62
> 0.62 + 0.5 LSB
Timing (minimum, ns)
5
2
40
5
2
16
16
1
5
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 51)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 51)
Offset Binary
Output Mode
D11 to D0
0000 0000 00
0000 0000 00
0000 0000 00
1111 1111 11
1111 1111 11
Rev. 0 | Page 24 of 28
Twos Complement Mode
D11 to D0
0000 0000 00
0000 0000 00
0000 0000 00
1111 1111 11
1111 1111 11
Gray Code Mode
(SPI Accessible)
D11 to D0
0000 0000 00
0000 0000 00
0000 0000 00
0000 0000 00
0000 0000 00
OR
1
0
0
0
1

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