MAX6621AUB+ MAXIM [Maxim Integrated Products], MAX6621AUB+ Datasheet - Page 13

• Manufacturer Part Number: MAX6621AUB+
• Description: PECI-to-I2C Translator
• Manufacturer: MAXIM [Maxim Integrated Products]

Table 18. Firmware Command
The result is a 16-bit word (low byte transmitted first,
high byte second) that contains the register that
caused ALERT to assert. An error (8103h) is returned
when there is no active ALERT.
The MAX6621 features a power-on reset (POR), bus
lockout reset, and a reset input (RESET). The power-on
reset monitors V
ance until V
MAX6621 monitors V
after power-up.
If an I
greater than 20ms, the MAX6621 asserts the internal
bus lockup reset that restarts itself in the default startup
condition.
The MAX6621 features a RESET input that allows users
to directly reset to the default startup conditions. Pull
RESET low for a minimum of 10ns for a valid reset. The
MAX6621 requires 100µs to be accessible after RESET
has been asserted.
Table 18 shows the command to read the firmware version.
Figure 5. 2-Wire Serial-Interface Timing Details
COMMAND
t
HD, STA
SDA
SCL
09h
2
CONDITION
C transaction starts and gets locked up for
START
Get firmware
version
CC
DESCRIPTION
CC
Version Information Command
t
LOW
______________________________________________________________________________________
passes the POR threshold. The
and holds all outputs in high imped-
CC
t
R
t
for brownout conditions even
SU, DAT
t
Bus Lockout Timeout Reset
HIGH
t
F
ReadWord
TYPE
t
HD, DAT
RESET
16 bit word
RESULT
RESET
Input
t
SU, STA
REPEATED START
CONDITION
The result is a 16-bit word (low byte transmitted first,
high byte second), e.g., 0100h for the MAX6621 firmware
version 1.0.
The MAX6621 operates as a slave that sends and
receives data through an I
face. The interface uses a serial-data line (SDA) and a
serial-clock line (SCL) to achieve bidirectional commu-
nication between master and slave. A master (typically
a microcontroller) initiates all data transfers to and from
the MAX6621 and generates the SCL clock that syn-
chronizes the data transfer (Figure 5).
The MAX6621 SCL and SDA lines operate as both
inputs and open-drain outputs. A pullup resistor is
required on SCL and SDA.
Each transmission consists of a START condition sent
by a master, followed by the MAX6621 7-bit slave
address, plus an R/W bit, one or more data bytes, and
finally a STOP condition (Figure 6). To write to a
MAX6621 register, a write transmission consists of a
START condition, followed by the MAX6621 7-bit slave
address plus R/W = 0, a register address byte, one
data byte, and finally a STOP condition. To read from a
MAX6621 register, a combined write and read trans-
missions are required. The first write transmission con-
sists of a START condition, followed by the MAX6621
7-bit slave address plus R/W = 0, a register address
byte, and finally a STOP condition that sets the register
to be read. The second read transmission consists of a
START condition, followed by the MAX6621 7-bit slave
address plus R/W = 1, one or more data bytes, and
finally a STOP condition that reads the data from the
PECI-to-I
t
HD, STA
2
C Translator
2
C-compatible, 2-wire inter-
t
SU, STO
Serial Interface
CONDITION
STOP
t
BUF
CONDITION
START
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