MAX6621AUB+ MAXIM [Maxim Integrated Products], MAX6621AUB+ Datasheet - Page 16

• Manufacturer Part Number: MAX6621AUB+
• Description: PECI-to-I2C Translator
• Manufacturer: MAXIM [Maxim Integrated Products]

A write to the MAX6621 consists of the transmission of
the MAX6621’s slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The com-
mand byte determines which register of the MAX6621
is to be written to by the next byte or read from during
the next read transmission. If a STOP condition is
detected after the command byte is received, the
MAX6621 takes no further action beyond setting the
register address.
The bytes received after the command byte are data
bytes. The data bytes go into the register of the
MAX6621 specified by the command byte. Only the last
data byte or word transmitted before a STOP condition
is stored by the device (Figure 10).
The MAX6621 is read using the MAX6621’s internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte is read. Thus, a read is initiated by first
configuring the MAX6621’s command byte by perform-
ing a write. The master can now read N consecutive
bytes from the MAX6621 with the first data byte being
read from the register addressed by the initialized com-
mand byte (Figure 10).
All MAX6621 I
checksum (PEC). The PEC is implemented in accor-
dance with the SMBus specification, versions 1.1 and
2. The MAX6621 accepts commands with or without
PEC. The PEC for device responses is optional and can
be disabled in the CONFIG0 register.
If the MAX6621 is operated on a 2-wire interface with
multiple masters, a master reading the MAX6621
should use a repeated START between the write that
sets the MAX6621’s address pointer, and the read(s)
that takes the data from the location(s) (Table 19). This
is because it is possible for master 2 to take over the
PECI-to-I
16
______________________________________________________________________________________
Message Format for Writing to the MAX6621
Message Format for Reading the MAX6621
Operation with Multiple Masters
2
C packets have an optional packet error
Applications Information
Packet Error Checksum (PEC)
2
C Translator
bus after master 1 has set up the MAX6621’s address
pointer, but before master 1 has read the data. If mas-
ter 2 subsequently changes the MAX6621’s address
pointer, master 1’s delayed read can be from an unex-
pected location. The use of multiple masters is not rec-
ommended.
The I
inputs AD0 and A1. Using the address inputs A0 and
A1, the base address can be configured from 48h to
4Bh (Table 19).
I
level to data and clock lines. There are tradeoffs
between power dissipation and speed, and a compro-
mise must be made in choosing pullup resistor values.
Every device connected to the bus introduces some
capacitance even when the device is not in operation.
I
to high (30% to 70%) for fast mode, which is defined for
a date rate of 400kbps (refer to the I
for details). To meet the rise time requirement, choose
pullup resistors so that the rise time t
x C
4.7kΩ resistor can be used. For a bus capacitance of
400pF, choose a pullup resistor less than 880Ω. Many
I
is not met. However, if the time it takes for the waveform
to rise becomes too slow, these waveforms are not rec-
ognized by the master.
Table 19. MAX6621 Slave Addresses
2
2
2
C specifies a minimum 300ns rise time to go from low
C devices work when the minimum specified rise time
C requires pullup resistors to provide a logic-high
10010:
A1:A0
BUS
0:0
0:1
1:0
1:1
2
C device address is configurable using address
< 300ns. For typical low bus capacitances, a
I
2
C ADDRESS
4Ah
4Bh
48h
49h
Choosing Pullup Resistors
90h, 91h
92h, 93h
94h, 95h,
A1 = 1 is a factory option
96h, 97h,
A1 = 1 is a factory option
I
2
INCLUDING R/W BIT
C Address Range
I
2
C ADDRESS
R
2
C specifications
= 0.85R
PULLUP