MAX6621AUB+ MAXIM [Maxim Integrated Products], MAX6621AUB+ Datasheet - Page 4

• Manufacturer Part Number: MAX6621AUB+
• Description: PECI-to-I2C Translator
• Manufacturer: MAXIM [Maxim Integrated Products]

PECI-to-I
TIMING CHARACTERISTICS (continued)
( Typical Application Circuit , V
values are at V
4
Note 1: All parameters are tested at T
Note 2: Guaranteed by design; not production tested.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
Note 4: C
Note 5: I
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 7: The MAX6621 must drive a more restrictive time to allow for quantized sampling errors by a client yet still attain the mini-
Note 8: The minimum and maximum bit times are relative to t
Note 9: Extended trace lengths can appear as additional nodes.
Note 10: The client may deassert its low idle drive prior to the falling edge of the first bit of the message by using the rising edge to
Note 11: The message stop is defined by two consecutive periods when the bus has no rising edge. Tolerance around this time is
Note 12: t
Bit Time Jitter
Change in Bit Time
High-Level Time for Logic-High
High-Level Time for Logic-Low
Client Asserts PECI High
During Logic-High
Rise Time
Fall Time
Hold Time
Stop Time
Maximum Dwell Time of the
PECI Client
Minimum PECI Low Time
Preceding a Message
_______________________________________________________________________________________
PARAMETER
the undefined region of SCL’s falling edge.
mum time less than 500µs. t
detect a message start. However, the time delay must be sufficient to qualify the rising edge as a true message rather than
a noise spike.
based on the t
SINK
SETUP
b
= total capacitance of one bus line in pF. t
CC
≤ 6mA. C
is not additive with t
= +3.3V, V
BIT-M
2
b
= total capacitance of one bus line in pF. t
C Translator
REF
error budget.
CC
= +1.0V, T
= +3V to +3.6V, V
SYMBOL
t
t
BIT, jitter
BIT, drift
t
t
t
STOP
t
SETUP
RESET
HOLD
STOP
BIT
t
t
t
SU
t
H1
H0
t
R
F
A
= +25°C. Specifications over temperature are guaranteed by design.
limits apply equally to t
. Rather, these times may overlap.
A
= +25°C.) (Note 2)
Between adjacent bits in an PECI message
header or data bytes after timing has been
negotiated
Across a PECI address or PECI message
bits as driven by MAX6621
(Note 8)
Measured from V
V
Measured from V
V
Time for client to maintain a low idle drive
after MAX6621 begins a message (Note 10)
A constant low level driven by MAX6621
(Notes 8, 11)
From the end of a ResetDevice command
to the next message to which the reset
client must be able to respond
If the prior t
the maximum t
t
SETUP
REF(nom)
REF(nom)
REF
= 1ms in this case (Note 12)
R
= +0.95V to +1.26V, T
-5% (Note 9)
+5% (Note 9)
and t
BIT
BIT
is not known by MAX6621,
CONDITIONS
F
BIT
OL
OH
measured between 0.3 x V
BIT-A
must be assumed and
defined in the timing negotiation pulse.
to V
to V
R
and t
and t
P
N
MAX,
MAX,
BIT-M
F
measured between 0.3 x V
A
.
= -20°C to +120°C, unless otherwise noted. Typical
CC
and 0.7 x V
MIN
0.6
0.2
0
2
IL
of the SCL signal) to bridge
CC
CC
TYP
0.75
0.3
1
2
2
and 0.7 x V
.
30/Node
5/Node
MAX
30 +
0.8
0.4
0.2
0.5
0.4
CC
.
x t
x t
x t
x t
UNITS
x t
x t
ms
BIT-M
BIT-M
ns
ns
BIT-X
%
%
BIT-1
BIT
BIT