MAX6621AUB+ MAXIM [Maxim Integrated Products], MAX6621AUB+ Datasheet - Page 14

• Manufacturer Part Number: MAX6621AUB+
• Description: PECI-to-I2C Translator
• Manufacturer: MAXIM [Maxim Integrated Products]

specified register. These write and read transmissions
can be joined using a repeated START even though the
MAX6621 7-bit slave address needs to be present pre-
ceding the R/W bits.
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 6).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 7).
PECI-to-I
Figure 6. Start and Stop Conditions
Figure 7. Bit Transfer
14
SDA
SCL
SDA
SCL
______________________________________________________________________________________
CONDITION
START
S
DATA LINE STABLE;
DATA VALID
2
Data Transfer and Acknowledge
CHANGE OF DATA
C Translator
ALLOWED
Start and Stop Conditions
CONDITION
STOP
P
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 8). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so that the SDA line is stable
low during the high period of the clock pulse. When the
master is transmitting to the MAX6621, the MAX6621
generates the acknowledge bit because the MAX6621
is the recipient. When the MAX6621 is transmitting to
the master, the master generates the acknowledge bit
because the master is the recipient.
The MAX6621 has a 7-bit long slave address (Figure 9).
The 8th bit following the 7-bit slave address is the R/W
bit. The R/W bit is low for a write command and high for
a read command.
Figure 8. Acknowledge
Figure 9. Slave Address
TRANSMITTER
SDA
SCL
RECEIVER
SDA BY
SDA BY
SCL
MSB
1
CONDITION
START
S
0
0
1
1
2
0
FOR ACKNOWLEDGEMENT
A1
CLOCK PULSE
A0
Slave Address
8
R/W
LSB
ACK
9