AD6640PCB AD [Analog Devices], AD6640PCB Datasheet - Page 14

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AD6640PCB

Manufacturer Part Number
AD6640PCB
Description
12-Bit, 65 MSPS IF Sampling A/D Converter
Manufacturer
AD [Analog Devices]
Datasheet
AD6640
The analog input range of the PCB is 0.5 volts (i.e., signal ac-
coupled to AD6640).
The encode signal may be generated using an onboard crystal
oscillator, U1. The oscillator is socketed and may be replaced
by an external encode source via J1. If an external source is
used, it should be a high quality TTL source. A transformer
converts the single-ended TTL signal to a differential clock (see
Encoding the AD6640). Since the encode is coupled with a
transformer, a sine wave could have been used; note, however,
that U5 requires TTL levels to function properly.
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Quantity
2
11
2
1
3
1
25
1
1
2
1
1
2
1
1
2
2
Reference
+5 VA, GND
C7–C9, C11–C17, C19
C4, C6
J3
J1, J2, J4
R1
R2–R14, R20–R25, R30–R35
R15
R16
T1, T2
U1
DUT
U3, U4
U5
C1, C18
C2, C3
CR1, CR2
Table I. AD6640ST/PCB Bill of Material
–14–
Description
Banana Jack
Ceramic Chip Capacitor 0805, 0.1 F
Tantalum Chip Capacitor 10 F
40-Pin Double Row Male Header
BNC Coaxial PCB Connector
Surface Mount Resistor 1206, 348
Surface Mount Resistor 1206, 348
Surface Mount Resistor 1206, 100
Surface Mount Resistor 1206, 270
Surface Mount Transformer Mini-Circuits T4–1T, 1:4 Ratio
Clock Oscillator (Optional)
AD6640AST 12-Bit–65 MSPS ADC Converter
74LCX574 Octal Latch
74LVQ00 Quad Two Input NAND Gate
Ceramic Chip Capacitor 0508, 0.01 F Low Inductance
Ceramic Chip Capacitor 0508, 0.1 F Low Inductance
1N2810 Schottky Diode
AD6640 output data is latched using 74LCX574 (U3, U4)
latches following 348 ohm series resistors. The resistors limit
the current that would otherwise flow due to the digital output
slew rate. The resistor value was chosen to represent a time
constant of ~25% of the data rate at 65 MHz. This reduces slew
rate while not appreciably distorting the data waveform. Data is
latched in a pipeline configuration; a rising edge generates the
new AD6640 data sample, latches the previous data at the con-
verter output, and strobes the external data register over J3.
NOTE: Power and ground must be applied to J3 to power the
digital logic section of the evaluation board.
REV. 0

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